EZ80F91NA050SC Zilog, EZ80F91NA050SC Datasheet - Page 146
EZ80F91NA050SC
Manufacturer Part Number
EZ80F91NA050SC
Description
IC ACCLAIM MCU 256KB 144-BGA
Manufacturer
Zilog
Series
eZ80® Acclaim!®r
Specifications of EZ80F91NA050SC
Core Processor
Z8
Core Size
8-Bit
Speed
50MHz
Connectivity
Ethernet, I²C, IrDA, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
32
Program Memory Size
256KB (256K x 8)
Program Memory Type
FLASH
Ram Size
16K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Oscillator Type
Internal
Operating Temperature
0°C ~ 70°C
Package / Case
144-LBGA
Data Bus Width
8 bit
Maximum Clock Frequency
50 MHz
Data Ram Size
16 KB
Number Of Programmable I/os
32
Number Of Timers
16 Bit
Operating Supply Voltage
3 V to 3.6 V
Mounting Style
SMD/SMT
Height
1.5 mm
Length
13 mm
Maximum Operating Temperature
+ 70 C
Minimum Operating Temperature
0 C
Width
13 mm
For Use With
269-4712 - KIT DEV ENCORE 32 SERIES269-4671 - BOARD ZDOTS SBC Z80ACCLAIM PLUS269-4561 - KIT DEV FOR EZ80F91 W/C-COMPILER269-4560 - KIT DEV FOR EZ80F91 W/C-COMPILER
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
Data Converters
-
Lead Free Status / Rohs Status
No RoHS Version Available
Other names
269-3251
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
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PS019215-0910
Timer Data Register—High Byte
The Timer x Data Register—High Byte returns the High byte of the count value of the
selected timer as it existed at the time that the Low byte was read. The Timer Data
Register—High Byte (see
current count value does not affect timer operation. To read the 16-bit data of the
current count value, {TMRx_DR_H[7:0], TMRx_DR_L[7:0]}, first read the Timer Data
Register—Low Byte followed by the Timer Data Register—High Byte. The Timer Data
Register—High Byte value is latched into temporary storage when a Read of the Timer
Data Register—Low Byte occurs.
This register shares its address with the corresponding timer reload register.
Table 58. Timer Data Register—High Byte
0069h, TMR2_DR_H = 0073h, TMR3_DR_H = 0078h)
Bit
Reset
CPU Access
Note: R = Read only.
Bit
Position
[7:0]
TMR_DR_H
Value
00h–FFh
Table
Description
These bits represent the High byte of the 2-byte timer data
value, {TMR
(msb) of the 16-bit timer data value. Bit 0 is bit 8 of the 16-bit
timer data value.
R
7
0
58) is read when the timer is in operation. Reading the
R
6
0
x
_DR_H[7:0], TMR
R
5
0
(TMR0_DR_H = 0064h, TMR1_DR_H =
R
4
0
x
_DR_L[7:0]}. Bit 7 is bit 15
R
3
0
Programmable Reload Timers
Product Specification
R
2
0
eZ80F91 MCU
R
1
0
R
0
0
137
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