EZ80F91NA050SC Zilog, EZ80F91NA050SC Datasheet - Page 225
![IC ACCLAIM MCU 256KB 144-BGA](/photos/12/15/121558/269-144-bga_sml.jpg)
EZ80F91NA050SC
Manufacturer Part Number
EZ80F91NA050SC
Description
IC ACCLAIM MCU 256KB 144-BGA
Manufacturer
Zilog
Series
eZ80® Acclaim!®r
Specifications of EZ80F91NA050SC
Core Processor
Z8
Core Size
8-Bit
Speed
50MHz
Connectivity
Ethernet, I²C, IrDA, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
32
Program Memory Size
256KB (256K x 8)
Program Memory Type
FLASH
Ram Size
16K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Oscillator Type
Internal
Operating Temperature
0°C ~ 70°C
Package / Case
144-LBGA
Data Bus Width
8 bit
Maximum Clock Frequency
50 MHz
Data Ram Size
16 KB
Number Of Programmable I/os
32
Number Of Timers
16 Bit
Operating Supply Voltage
3 V to 3.6 V
Mounting Style
SMD/SMT
Height
1.5 mm
Length
13 mm
Maximum Operating Temperature
+ 70 C
Minimum Operating Temperature
0 C
Width
13 mm
For Use With
269-4712 - KIT DEV ENCORE 32 SERIES269-4671 - BOARD ZDOTS SBC Z80ACCLAIM PLUS269-4561 - KIT DEV FOR EZ80F91 W/C-COMPILER269-4560 - KIT DEV FOR EZ80F91 W/C-COMPILER
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
Data Converters
-
Lead Free Status / Rohs Status
No RoHS Version Available
Other names
269-3251
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
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PS019215-0910
Operating Modes
must send this repeated START condition or STOP condition at the same position in the
format frame. In other words, arbitration is not allowed between:
•
•
•
Clock Synchronization for Handshake
The clock-synchronizing mechanism functions as a handshake, enabling receivers to cope
with fast data transfers, on either a byte or a bit level. The byte level allows a device to
receive a byte of data at a fast rate, but allows the device more time to store the received
byte or to prepare another byte for transmission. Slaves hold the SCL line Low after recep-
tion and acknowledge the byte, forcing the master into a Wait state until the slave is ready
for the next byte transfer in a handshake procedure.
Master Transmit
In MASTER TRANSMIT mode, the I
Enter MASTER TRANSMIT mode by setting the STA bit in the I2C_CTL register to 1.
The I
When a START condition is transmitted, the IFLG bit is 1 and the status code in the
I2C_SR register is
loaded with either a 7-bit slave address or the first part of a 10-bit slave address, with the
lsb cleared to 0 to specify TRANSMIT mode. The IFLG bit must now be cleared to 0 to
prompt the transfer to continue.
After the 7-bit slave address (or the first part of a 10-bit address) plus the Write bit are
transmitted, the IFLG is set again. A number of status codes are possible in the I2C_SR
register. See
A repeated START condition and a data bit.
A STOP condition and a data bit.
A repeated START condition and a STOP condition.
2
C then tests the I
Table 118
08h
2
. Before this interrupt is serviced, the I2C_DR register must be
on page 217.
C bus and transmits a START condition when the bus is free.
2
C transmits a number of bytes to a slave receiver.
Product Specification
I
2
C Serial I/O Interface
216
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