EZ80F91NA050SC Zilog, EZ80F91NA050SC Datasheet - Page 90
EZ80F91NA050SC
Manufacturer Part Number
EZ80F91NA050SC
Description
IC ACCLAIM MCU 256KB 144-BGA
Manufacturer
Zilog
Series
eZ80® Acclaim!®r
Specifications of EZ80F91NA050SC
Core Processor
Z8
Core Size
8-Bit
Speed
50MHz
Connectivity
Ethernet, I²C, IrDA, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
32
Program Memory Size
256KB (256K x 8)
Program Memory Type
FLASH
Ram Size
16K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Oscillator Type
Internal
Operating Temperature
0°C ~ 70°C
Package / Case
144-LBGA
Data Bus Width
8 bit
Maximum Clock Frequency
50 MHz
Data Ram Size
16 KB
Number Of Programmable I/os
32
Number Of Timers
16 Bit
Operating Supply Voltage
3 V to 3.6 V
Mounting Style
SMD/SMT
Height
1.5 mm
Length
13 mm
Maximum Operating Temperature
+ 70 C
Minimum Operating Temperature
0 C
Width
13 mm
For Use With
269-4712 - KIT DEV ENCORE 32 SERIES269-4671 - BOARD ZDOTS SBC Z80ACCLAIM PLUS269-4561 - KIT DEV FOR EZ80F91 W/C-COMPILER269-4560 - KIT DEV FOR EZ80F91 W/C-COMPILER
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
Data Converters
-
Lead Free Status / Rohs Status
No RoHS Version Available
Other names
269-3251
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
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Table 25. Motorola Bus Mode Read States
PS019215-0910
STATE S0
STATE S1
STATE S2
STATE S3
STATE S4
STATE S5
The Read cycle starts in state S0. The CPU drives R/W High to identify a Read cycle.
Entering state S1, the CPU drives a valid address on the address bus, ADDR[23:0].
During state S3, no bus signals are altered.
During state S4, the CPU waits for a cycle termination signal DTACK (WAIT), a peripheral
During state S5, no bus signals are altered.
On the rising edge of state S2, the CPU asserts AS and DS.
signal. If the termination signal is not asserted at least one full CPU clock period prior to the
rising clock edge at the end of S4, the CPU inserts WAIT (T
asserted. Each wait state is a full bus mode cycle.
During Write operations, the Motorola bus mode employs eight states—S0, S1, S2, S3,
S4, S5, S6, and S7 as listed in
eZ80 Bus Mode
Signals (Pins)
ADDR[23:0]
DATA[7:0]
INSTRD
MREQ
IORQ
WAIT
WR
RD
Figure 17. Motorola Bus Mode Signal and Pin Mapping
Table
Bus Mode
Controller
25.
WAIT
Motorola Bus
Signal Equvalents
AS
DS
R/W
DTACK
MREQ
IORQ
ADDR[23:0]
DATA[7:0]
) states until DTACK is
Chip Selects and Wait States
Product Specification
eZ80F91 MCU
81
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