EZ80F91NA050SC Zilog, EZ80F91NA050SC Datasheet - Page 208
EZ80F91NA050SC
Manufacturer Part Number
EZ80F91NA050SC
Description
IC ACCLAIM MCU 256KB 144-BGA
Manufacturer
Zilog
Series
eZ80® Acclaim!®r
Specifications of EZ80F91NA050SC
Core Processor
Z8
Core Size
8-Bit
Speed
50MHz
Connectivity
Ethernet, I²C, IrDA, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
32
Program Memory Size
256KB (256K x 8)
Program Memory Type
FLASH
Ram Size
16K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Oscillator Type
Internal
Operating Temperature
0°C ~ 70°C
Package / Case
144-LBGA
Data Bus Width
8 bit
Maximum Clock Frequency
50 MHz
Data Ram Size
16 KB
Number Of Programmable I/os
32
Number Of Timers
16 Bit
Operating Supply Voltage
3 V to 3.6 V
Mounting Style
SMD/SMT
Height
1.5 mm
Length
13 mm
Maximum Operating Temperature
+ 70 C
Minimum Operating Temperature
0 C
Width
13 mm
For Use With
269-4712 - KIT DEV ENCORE 32 SERIES269-4671 - BOARD ZDOTS SBC Z80ACCLAIM PLUS269-4561 - KIT DEV FOR EZ80F91 W/C-COMPILER269-4560 - KIT DEV FOR EZ80F91 W/C-COMPILER
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
Data Converters
-
Lead Free Status / Rohs Status
No RoHS Version Available
Other names
269-3251
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
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Table 110. Infrared Encoder/Decoder Control Registers
PS019215-0910
Bit
Reset
CPU Access
Note:
Bit
Position
[7:4]
MIN_PULSE
3
2
LOOP_BACK
1
IR_RxEN
0
IR_EN
R = Read only; R/W = Read/Write.
Infrared Encoder/Decoder Register
After a RESET, the Infrared Encoder/Decoder Register is set to its default value. Any
Writes to unused register bits are ignored and reads return a value of 0. The IR_CTL regis-
ter is listed in
Value
0000
1h-Fh
0
0
1
0
1
0
1
Description
Minimum receive pulse width control. When this field is equal to
0x0, the IrDA decoder uses edge detection to accept arbitrarily
narrow (that is, short) input pulses.
When not equal to 0x0, this field forms the most-significant four
bits of the 6-bit down-counter used to determine if an input
pulse will be ignored because it is too narrow. The lower two
counter bits are hard-coded to load with 0x3, resulting in a total
down-count equal to ((IR_CTL[4:0]MIN_PULSE * 4) + 3). To be
accepted, input pulses must have a width greater than or equal
to the down-count value times the system clock period.
Reserved.
Internal LOOP BACK mode is disabled.
Internal LOOP BACK mode is enabled.
IR_TxD output is inverted and connected to IR_RxD input for
internal loop back testing.
IR_RxD data is ignored.
IR_RxD data is passed to UART0
Endec is disabled.
Endec is enabled.
R/W
7
0
Table
R/W
6
0
110.
R/W
5
0
R/W
4
0
R
3
0
R
x
D
.
(IR_CTL = 00BFh)
R/W
2
0
R/W
1
0
Product Specification
Infrared Encoder/Decoder
R/W
0
0
199
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