EZ80F91NA050SC Zilog, EZ80F91NA050SC Datasheet - Page 203
EZ80F91NA050SC
Manufacturer Part Number
EZ80F91NA050SC
Description
IC ACCLAIM MCU 256KB 144-BGA
Manufacturer
Zilog
Series
eZ80® Acclaim!®r
Specifications of EZ80F91NA050SC
Core Processor
Z8
Core Size
8-Bit
Speed
50MHz
Connectivity
Ethernet, I²C, IrDA, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
32
Program Memory Size
256KB (256K x 8)
Program Memory Type
FLASH
Ram Size
16K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Oscillator Type
Internal
Operating Temperature
0°C ~ 70°C
Package / Case
144-LBGA
Data Bus Width
8 bit
Maximum Clock Frequency
50 MHz
Data Ram Size
16 KB
Number Of Programmable I/os
32
Number Of Timers
16 Bit
Operating Supply Voltage
3 V to 3.6 V
Mounting Style
SMD/SMT
Height
1.5 mm
Length
13 mm
Maximum Operating Temperature
+ 70 C
Minimum Operating Temperature
0 C
Width
13 mm
For Use With
269-4712 - KIT DEV ENCORE 32 SERIES269-4671 - BOARD ZDOTS SBC Z80ACCLAIM PLUS269-4561 - KIT DEV FOR EZ80F91 W/C-COMPILER269-4560 - KIT DEV FOR EZ80F91 W/C-COMPILER
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
Data Converters
-
Lead Free Status / Rohs Status
No RoHS Version Available
Other names
269-3251
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
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Table 108. UART Scratch Pad Registers
PS019215-0910
Bit
Position
3
DDCD
2
TERI
1
DDSR
0
DCTS
Bit
Reset
CPU Access
Note: R/W = Read/Write.
Bit
Position
[7:0]
SPR
Value
00h–FFh
UART Scratch Pad Register
The UARTx_SPR register is used by the system as a general-purpose Read/Write register.
See
Value
0–1
0–1
0–1
0–1
Table
Description
UART scratch pad register is available for use as a general-
purpose Read/Write register. In multi-drop 9 bit mode, this
register is used to store the address value.
Description
Delta Status Change of DCD.
This bit is set to 1 whenever the DCDx pin changes state. This
bit is reset to 0 when the UARTx_MSR register is read.
Trailing Edge Change on RI.
This bit is set to 1 whenever a falling edge is detected on the
RIx pin. This bit is reset to 0 when the UARTx_MSR register is
read.
Delta Status Change of DSR.
This bit is set to 1 whenever the DSRx pin changes state. This
bit is reset to 0 when the UARTx_MSR register is read.
Delta Status Change of CTS.
This bit is set to 1 whenever the CTSx pin changes state.
This bit is reset to 0 when the UARTx_MSRs register is read.
R/W
108.
7
0
R/W
6
0
R/W
5
0
(UART0_SPR = 00C7h, UART1_SPR = 00D7h)
R/W
4
0
R/W
3
0
Universal Asynchronous Receiver/Transmitter
R/W
2
0
R/W
1
0
Product Specification
R/W
0
0
eZ80F91 MCU
194
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