EZ80F91NA050SC Zilog, EZ80F91NA050SC Datasheet - Page 57

• Manufacturer Part Number: EZ80F91NA050SC
• Description: IC ACCLAIM MCU 256KB 144-BGA
• Manufacturer: Zilog
• Series: eZ80® Acclaim!®r

Specifications of EZ80F91NA050SC

• Core Processor: Z8
• Core Size: 8-Bit
• Speed: 50MHz
• Connectivity: Ethernet, I²C, IrDA, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 32
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Oscillator Type: Internal
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 144-LBGA
• Data Bus Width: 8 bit
• Maximum Clock Frequency: 50 MHz
• Data Ram Size: 16 KB
• Number Of Programmable I/os: 32
• Number Of Timers: 16 Bit
• Operating Supply Voltage: 3 V to 3.6 V
• Mounting Style: SMD/SMT
• Height: 1.5 mm
• Length: 13 mm
• Maximum Operating Temperature: + 70 C
• Minimum Operating Temperature: 0 C
• Width: 13 mm
• For Use With: 269-4712 - KIT DEV ENCORE 32 SERIES269-4671 - BOARD ZDOTS SBC Z80ACCLAIM PLUS269-4561 - KIT DEV FOR EZ80F91 W/C-COMPILER269-4560 - KIT DEV FOR EZ80F91 W/C-COMPILER
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: No RoHS Version Available
• Other names: 269-3251

Table 5. Clock Peripheral Power-Down Register 2
PS019215-0910
Bit
Reset
CPU Access
Note: R = Read Only; R/W = Read/Write.
Bit Position
7
PHI_OFF
6 VBO_OFF
[5:4]
3
TIMER3_OFF
2
TIMER2_OFF
1
TIMER1_OFF
0
TIMER0_OFF
Value Description
1
0
1
0
000
1
0
1
0
1
0
1
0
PHI Clock output is disabled (output is high-impedance).
PHI Clock output is enabled.
Voltage Brownout detection circuit is disabled. This reduces
DC current consumption in situations where VBO detection is
not necessary. Power-On Reset functionality is not affected by
this setting.
VBO detection circuit is enabled.
Reserved.
System clock to TIMER3 is powered down.
System clock to TIMER3 is powered up.
System clock to TIMER2 is powered down.
System clock to TIMER2 is powered up.
System clock to TIMER1 is powered down.
System clock to TIMER1 is powered up.
System clock to TIMER0 is powered down.
System clock to TIMER0 is powered up.
R/W
7
0
R/W
6
0
R
5
0
R
4
0
(CLK_PPD2 = 00DCh)
R/W
3
0
R/W
2
0
R/W
1
0
Product Specification
R/W
0
0
Low-Power Modes
48