EZ80F91NA050SC Zilog, EZ80F91NA050SC Datasheet - Page 276

• Manufacturer Part Number: EZ80F91NA050SC
• Description: IC ACCLAIM MCU 256KB 144-BGA
• Manufacturer: Zilog
• Series: eZ80® Acclaim!®r

Specifications of EZ80F91NA050SC

• Core Processor: Z8
• Core Size: 8-Bit
• Speed: 50MHz
• Connectivity: Ethernet, I²C, IrDA, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 32
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Oscillator Type: Internal
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 144-LBGA
• Data Bus Width: 8 bit
• Maximum Clock Frequency: 50 MHz
• Data Ram Size: 16 KB
• Number Of Programmable I/os: 32
• Number Of Timers: 16 Bit
• Operating Supply Voltage: 3 V to 3.6 V
• Mounting Style: SMD/SMT
• Height: 1.5 mm
• Length: 13 mm
• Maximum Operating Temperature: + 70 C
• Minimum Operating Temperature: 0 C
• Width: 13 mm
• For Use With: 269-4712 - KIT DEV ENCORE 32 SERIES269-4671 - BOARD ZDOTS SBC Z80ACCLAIM PLUS269-4561 - KIT DEV FOR EZ80F91 W/C-COMPILER269-4560 - KIT DEV FOR EZ80F91 W/C-COMPILER
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: No RoHS Version Available
• Other names: 269-3251

PS019215-0910
PLL Normal Operation
for the number of consecutive reference clock cycles. The lock criteria is selected in the
PLL Control Register, PLL_CTL0[LDS_CTL]. When the locked condition is met, this
block outputs a logic High signal (lock) that interrupts the CPU.
By default (after system reset) the PLL is disabled and SCLK = XTAL oscillator. Ensuring
proper loop filter, supply voltages and external oscillator are correctly configured, the PLL
is enabled. The SCLK/Timer cannot choose the PLL as its source until the PLL is locked,
as determined by the lock detect block. By forcing the PLL to be locked prior to enabling
the PLL as a SCLK/Timer source, it is assured to be stable and accurate.
Figure 58
displays the programming flow for normal PLL operation.
Figure 58. Normal PLL Programming Flow
Set SCLK MUX to PLL (PLL_CTL0)
{Charge Pump & Lock criteria}
PLL_DIV_L then PLL_DIV_H
Disable Lock Interrupt Mask
Execute Application Code
Execute instructions with
SCLK = XTAL Oscillator
Upon Lock Interrupt:
{Interrupts & PLL}
POR/System
{PLL Divider}
(PLL_CTL1)
PLL_CTL0
PLL_CTL1
Program:
Enable:
Reset
Product Specification
Phase-Locked Loop
eZ80F91 MCU
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