EZ80F91NA050SC Zilog, EZ80F91NA050SC Datasheet - Page 210
![IC ACCLAIM MCU 256KB 144-BGA](/photos/12/15/121558/269-144-bga_sml.jpg)
EZ80F91NA050SC
Manufacturer Part Number
EZ80F91NA050SC
Description
IC ACCLAIM MCU 256KB 144-BGA
Manufacturer
Zilog
Series
eZ80® Acclaim!®r
Specifications of EZ80F91NA050SC
Core Processor
Z8
Core Size
8-Bit
Speed
50MHz
Connectivity
Ethernet, I²C, IrDA, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
32
Program Memory Size
256KB (256K x 8)
Program Memory Type
FLASH
Ram Size
16K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Oscillator Type
Internal
Operating Temperature
0°C ~ 70°C
Package / Case
144-LBGA
Data Bus Width
8 bit
Maximum Clock Frequency
50 MHz
Data Ram Size
16 KB
Number Of Programmable I/os
32
Number Of Timers
16 Bit
Operating Supply Voltage
3 V to 3.6 V
Mounting Style
SMD/SMT
Height
1.5 mm
Length
13 mm
Maximum Operating Temperature
+ 70 C
Minimum Operating Temperature
0 C
Width
13 mm
For Use With
269-4712 - KIT DEV ENCORE 32 SERIES269-4671 - BOARD ZDOTS SBC Z80ACCLAIM PLUS269-4561 - KIT DEV FOR EZ80F91 W/C-COMPILER269-4560 - KIT DEV FOR EZ80F91 W/C-COMPILER
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
Data Converters
-
Lead Free Status / Rohs Status
No RoHS Version Available
Other names
269-3251
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
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Serial Peripheral Interface
PS019215-0910
DATAIN
ENABLE
DATAIN
CLKIN
The Serial Peripheral Interface (SPI) is a synchronous interface allowing several SPI-type
devices to be interconnected. The SPI is a full-duplex, synchronous, character-oriented
communication channel that employs a four-wire interface. The SPI block consists of a
transmitter, receiver, baud rate generator, and control unit. During an SPI transfer, data is
sent and received simultaneously by both the master and the slave SPI devices.
In a serial peripheral interface, separate signals are required for data and clock. The SPI is
configured either as a master or as a slave. The connection of two SPI devices (one master
and one slave) and the direction of data transfer is displayed in
SS
MISO
SS
MOSI
SCK
Bit 0
Bit 0
Bit 0
Baud Rate
Generator
8-Bit Shift Register
Figure 40. SPI Master Device
8-Bit Shift Register
Figure 41. SPI Slave Device
MASTER
SLAVE
Bit 7
Bit 7
MOSI
MISO
SCK
Figure 40
Product Specification
Serial Peripheral Interface
DATAOUT
CLKOUT
DATAOUT
and
eZ80F91 MCU
Figure
41.
201
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