EZ80F91NA050SC Zilog, EZ80F91NA050SC Datasheet - Page 228
EZ80F91NA050SC
Manufacturer Part Number
EZ80F91NA050SC
Description
IC ACCLAIM MCU 256KB 144-BGA
Manufacturer
Zilog
Series
eZ80® Acclaim!®r
Specifications of EZ80F91NA050SC
Core Processor
Z8
Core Size
8-Bit
Speed
50MHz
Connectivity
Ethernet, I²C, IrDA, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
32
Program Memory Size
256KB (256K x 8)
Program Memory Type
FLASH
Ram Size
16K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Oscillator Type
Internal
Operating Temperature
0°C ~ 70°C
Package / Case
144-LBGA
Data Bus Width
8 bit
Maximum Clock Frequency
50 MHz
Data Ram Size
16 KB
Number Of Programmable I/os
32
Number Of Timers
16 Bit
Operating Supply Voltage
3 V to 3.6 V
Mounting Style
SMD/SMT
Height
1.5 mm
Length
13 mm
Maximum Operating Temperature
+ 70 C
Minimum Operating Temperature
0 C
Width
13 mm
For Use With
269-4712 - KIT DEV ENCORE 32 SERIES269-4671 - BOARD ZDOTS SBC Z80ACCLAIM PLUS269-4561 - KIT DEV FOR EZ80F91 W/C-COMPILER269-4560 - KIT DEV FOR EZ80F91 W/C-COMPILER
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
Data Converters
-
Lead Free Status / Rohs Status
No RoHS Version Available
Other names
269-3251
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
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Table 120. I
PS019215-0910
Code
28h
30h
38h
I
Data byte transmitted,
ACK received
Data byte transmitted,
ACK not received
Arbitration lost
2
2
C State
C Master Transmit Status Codes For Data Bytes
When all bytes are transmitted, the microcontroller must write a 1 to the STP bit in the
I2C_CTL register. The I
to an idle state.
Master Receive
In MASTER RECEIVE mode, the I
transmitter.
After the START condition is transmitted, the IFLG bit is 1 and the status code
loaded into the I2C_SR register. The I2C_DR register must be loaded with the slave
address (or the first part of a 10-bit slave address), with the lsb set to 1 to signify a Read.
The IFLG bit must be cleared to 0 as a prompt for the transfer to continue.
When the 7-bit slave address (or the first part of a 10-bit address) and the Read bit are
transmitted, the IFLG bit is set and one of the status codes listed in
is loaded into the I2C_SR register.
Microcontroller Response
Write byte to data,
clear IFLG
Or set STA, clear IFLG
Or set STP, clear IFLG
Or set STA & STP,
clear IFLG
Same as code 28h
Clear IFLG
Or set STA, clear IFLG
2
C then transmits a STOP condition, clears the STP bit and returns
2
C receives a number of bytes from a slave
Next I
Transmit data byte,
receive ACK
Transmit repeated START
Transmit STOP
Transmit START then STOP
Same as code 28h
Return to idle
Transmit START when bus free
2
C Action
Product Specification
Table 121
I
2
C Serial I/O Interface
on page 220
08h
is
219
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