MC908AZ60ACFU Freescale Semiconductor, MC908AZ60ACFU Datasheet

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MC908AZ60ACFU

Manufacturer Part Number
MC908AZ60ACFU
Description
IC MCU FLASH 8.4MHZ 60K 64QFP
Manufacturer
Freescale Semiconductor
Series
HC08r
Datasheet

Specifications of MC908AZ60ACFU

Core Processor
HC08
Core Size
8-Bit
Speed
8.4MHz
Connectivity
CAN, SCI, SPI
Peripherals
LVD, POR, PWM
Number Of I /o
52
Program Memory Size
60KB (60K x 8)
Program Memory Type
FLASH
Eeprom Size
1K x 8
Ram Size
2K x 8
Voltage - Supply (vcc/vdd)
4.5 V ~ 5.5 V
Data Converters
A/D 15x8b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
64-QFP
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant

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MC68HC908AZ60A
MC68HC908AS60A
MC68HC908AZ60E
Data Sheet
M68HC08
Microcontrollers
MC68HC908AZ60A
Rev. 6
05/2006
freescale.com

MC908AZ60ACFU Summary of contents

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MC68HC908AZ60A MC68HC908AS60A MC68HC908AZ60E Data Sheet M68HC08 Microcontrollers MC68HC908AZ60A Rev. 6 05/2006 freescale.com ...

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...

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... Your printed copy may be an earlier revision. To verify you have the latest information available, refer to: http://freescale.com Freescale™ and the Freescale logo are trademarks of Freescale Semiconductor, Inc. This product incorporates SuperFlash® technology licensed from SST. © Freescale Semiconductor, Inc., 2006. All rights reserved. ...

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... MC68HC908AZ60A • MC68HC908AS60A • MC68HC908AS60E Data Sheet, Rev Freescale Semiconductor ...

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... Chapter 18 Serial Communications Interface (SCI 177 Chapter 19 Serial Peripheral Interface (SPI 205 Chapter 20 Timer Interface Module B (TIMB 227 Chapter 21 Programmable Interrupt Timer (PIT 243 Chapter 22 Input/Output Ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 249 Chapter 23 MSCAN Controller (MSCAN08 267 MC68HC908AZ60A • MC68HC908AS60A • MC68HC908AS60E Data Sheet, Rev. 6 Freescale Semiconductor 5 ...

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... Chapter 25 Timer Interface Module A (TIMA 307 Chapter 26 Analog-to-Digital Converter (ADC .327 Chapter 27 Byte Data Link Controller (BDLC 335 Chapter 28 Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 365 Appendix A MC68HC908AS60 and MC68HC908AZ60 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 381 Appendix B MC68HC908AZ60E . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 385 Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 401 Glossary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 405 MC68HC908AZ60A • MC68HC908AS60A • MC68HC908AS60E Data Sheet, Rev Freescale Semiconductor ...

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... Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 2.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 2.2 I/O Section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 2.3 Additional Status and Control Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 2.4 Vector Addresses and Priority . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 3.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 3.2 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 MC68HC908AZ60A • MC68HC908AS60A • MC68HC908AS60E Data Sheet, Rev. 6 Freescale Semiconductor Chapter 1 General Description and DDA ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 SSA ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 DDAREF ...

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... Program/Erase Using AUTO Bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 6.4.5.2 EEPROM-1 Programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76 6.4.5.3 EEPROM-1 Erasing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77 6.5 EEPROM-1 Register Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78 6.5.1 EEPROM-1 Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78 6.5.2 EEPROM-1 Array Configuration Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79 MC68HC908AZ60A • MC68HC908AS60A • MC68HC908AS60E Data Sheet, Rev Chapter 4 FLASH-1 Memory Chapter 5 FLASH-2 Memory Chapter 6 EEPROM-1 Memory Freescale Semiconductor ...

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... Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103 8.5.2 Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103 8.6 CPU During Break Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103 8.7 Instruction Set Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104 8.8 Opcode Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109 MC68HC908AZ60A • MC68HC908AS60A • MC68HC908AS60E Data Sheet, Rev. 6 Freescale Semiconductor Chapter 7 EEPROM-2 Memory Chapter 8 Central Processor Unit (CPU) 9 ...

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... Programming the PLL 132 10.3.2.5 Special Programming Exceptions 133 10.3.3 Base Clock Selector Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133 10.3.4 CGM External Connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 134 MC68HC908AZ60A • MC68HC908AS60A • MC68HC908AS60E Data Sheet, Rev Chapter 9 System Integration Module (SIM) Chapter 10 Clock Generator Module (CGM) Freescale Semiconductor ...

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... Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 151 13.5 Break Module Registers 151 13.5.1 Break Status and Control Register 152 13.5.2 Break Address Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 152 MC68HC908AZ60A • MC68HC908AS60A • MC68HC908AS60E Data Sheet, Rev. 6 Freescale Semiconductor ). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135 DDA Chapter 11 Configuration Register (CONFIG-1) Chapter 12 Configuration Register (CONFIG-2) Chapter 13 ...

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... LVI Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 169 16.5 LVI Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 169 16.6 Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 169 16.6.1 Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 169 16.6.2 Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 170 MC68HC908AZ60A • MC68HC908AS60A • MC68HC908AS60E Data Sheet, Rev Chapter 14 Monitor ROM (MON) Chapter 15 Computer Operating Properly (COP) Chapter 16 Low-Voltage Inhibit (LVI) Freescale Semiconductor ...

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... SCI Control Register 196 18.8.4 SCI Status Register 197 18.8.5 SCI Status Register 200 18.8.6 SCI Data Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 201 18.8.7 SCI Baud Rate Register 201 MC68HC908AZ60A • MC68HC908AS60A • MC68HC908AS60E Data Sheet, Rev. 6 Freescale Semiconductor Chapter 17 External Interrupt Module (IRQ) Chapter 18 13 ...

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... Pulse Width Modulation (PWM 231 20.3.4.1 Unbuffered PWM Signal Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 231 20.3.4.2 Buffered PWM Signal Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 232 20.3.4.3 PWM Initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 233 MC68HC908AZ60A • MC68HC908AS60A • MC68HC908AS60E Data Sheet, Rev Chapter 19 Serial Peripheral Interface (SPI) Chapter 20 Timer Interface Module B (TIMB) Freescale Semiconductor ...

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... Port D Data Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 256 22.5.2 Data Direction Register 257 22.6 Port 258 22.6.1 Port E Data Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 258 22.6.2 Data Direction Register 259 MC68HC908AZ60A • MC68HC908AS60A • MC68HC908AS60E Data Sheet, Rev. 6 Freescale Semiconductor Chapter 21 Programmable Interrupt Timer (PIT) Chapter 22 Input/Output Ports 15 ...

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... MSCAN08 Bus Timing Register 289 23.13.4 MSCAN08 Bus Timing Register 290 23.13.5 MSCAN08 Receiver Flag Register (CRFLG 291 23.13.6 MSCAN08 Receiver Interrupt Enable Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 293 23.13.7 MSCAN08 Transmitter Flag Register 294 MC68HC908AZ60A • MC68HC908AS60A • MC68HC908AS60E Data Sheet, Rev Chapter 23 MSCAN Controller (MSCAN08) Freescale Semiconductor ...

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... TIMA Counter Registers 318 25.8.3 TIMA Counter Modulo Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 319 25.8.4 TIMA Channel Status and Control Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 320 25.8.5 TIMA Channel Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 323 MC68HC908AZ60A • MC68HC908AS60A • MC68HC908AS60E Data Sheet, Rev. 6 Freescale Semiconductor Chapter 24 Keyboard Module (KBI) Chapter 25 Timer Interface Module A (TIMA) 17 ...

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... Rx and Tx Shift Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 350 27.5.3 Rx and Tx Shadow Registers 350 MC68HC908AZ60A • MC68HC908AS60A • MC68HC908AS60E Data Sheet, Rev Chapter 26 Analog-to-Digital Converter (ADC) )/ADC Voltage Reference Pin (V DDAREF )/ADC Voltage Reference Low Pin (V SSA Chapter 27 Byte Data Link Controller (BDLC 330 REFH . . . . . . . . . . . . 330 REFL) Freescale Semiconductor ...

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... BDLC Transmitter DC Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 377 28.1.18 BDLC Receiver DC Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 377 28.2 Mechanical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 378 28.2.1 51-Pin Plastic Leaded Chip Carrier (PLCC 378 28.2.2 64-Pin Quad Flat Pack (QFP 379 MC68HC908AZ60A • MC68HC908AS60A • MC68HC908AS60E Data Sheet, Rev. 6 Freescale Semiconductor Chapter 28 Electrical Specifications 19 ...

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... Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 397 B.6.1 MC Order Numbers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 397 B.7 Configuration Register (CONFIG-3 398 B.8 SCI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 398 B.9 MSCAN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 398 B.10 ADC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 399 Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 401 Glossary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 405 MC68HC908AZ60A • MC68HC908AS60A • MC68HC908AS60E Data Sheet, Rev Appendix A Appendix B MC68HC908AZ60E Revision History Glossary Freescale Semiconductor ...

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... Low-Voltage Detection with Optional Reset – Illegal Opcode Detection with Optional Reset – Illegal Address Detection with Optional Reset • Low-Power Design (Fully Static with Stop and Wait Modes) MC68HC908AZ60A • MC68HC908AS60A • MC68HC908AS60E Data Sheet, Rev. 6 Freescale Semiconductor Appendix B MC68HC908AZ60E. 21 ...

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... Binary-Coded Decimal (BCD) Instructions • Optimization for Controller Applications • C Language Support 1.3 MCU Block Diagram Figure 1-1 shows the structure of the MC68HC908AZ60A. Figure 1-2 shows the structure of the MC68HC908AS60A. MC68HC908AZ60A • MC68HC908AS60A • MC68HC908AS60E Data Sheet, Rev Freescale Semiconductor ...

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M68HC08 CPU CPU ARITHMETIC/LOGIC REGISTERS UNIT (ALU) CONTROL AND STATUS REGISTERS — 62 BYTES USER FLASH — 60 kBYTES USER RAM — 2048BYTES USER EEPROM — 1024 BYTES MONITOR ROM — 256 BYTES USER FLASH VECTOR SPACE — 52 BYTES ...

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M68HC08 CPU CPU ARITHMETIC/LOGIC REGISTERS UNIT (ALU) CONTROL AND STATUS REGISTERS — 62 BYTES USER FLASH — 60 kBYTES USER RAM — 2048BYTES USER EEPROM — 1024 BYTES MONITOR ROM — 256 BYTES USER FLASH VECTOR SPACE — 52 BYTES ...

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... PTF1/TACH3 5 PTF2/TACH4 6 PTF3/TACH5 7 PTF4/TBCH0 8 CANRx 9 CANTx 10 PTF5/TBCH1 11 PTF6 12 PTE0/TxD 13 PTE1/RxD 14 PTE2/TACH0 15 PTE3/TACH1 16 Figure 1-3. MC68HC908AZ60A (64-Pin QFP) MC68HC908AZ60A • MC68HC908AS60A • MC68HC908AS60E Data Sheet, Rev. 6 Freescale Semiconductor Pin Assignments PTH0/KBD3 48 PTD3/ATD11 47 PTD2/ATD10 REFL V 44 DDAREF PTD1/ATD9 43 PTD0/ATD8 42 PTB7/ATD7 41 PTB6/ATD6 40 PTB5/ATD5 39 PTB4/ATD4 ...

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... PTF4 8 BDRxD 9 BDTxD 10 PTF5 11 PTF6 12 PTE0/TxD 13 PTE1/RxD 14 PTE2/TACH0 15 PTE3/TACH1 16 Figure 1-4. MC68HC908AS60A (64-Pin QFP) MC68HC908AZ60A • MC68HC908AS60A • MC68HC908AS60E Data Sheet, Rev PTH0/KBD3 48 PTD3/ATD11 47 PTD2/ATD10 REFL V 44 DDAREF PTD1/ATD9 43 PTD0/ATD8 42 PTB7/ATD7 41 PTB6/ATD6 40 PTB5/ATD5 39 PTB4/ATD4 38 PTB3/ATD3 37 PTB2/ATD2 36 PTB1/ATD1 35 PTB0/ATD0 34 PTA7 33 Freescale Semiconductor ...

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... IRQ 9 RST 10 PTF0/TACH2 11 PTF1/TACH3 12 PTF2/TACH4 13 PTF3/TACH5 14 BDRxD 15 BDTxD 16 PTE0/TxD 17 PTE1/RxD 18 PTE2/TACH0 19 PTE3/TACH1 20 Figure 1-5. MC68HC908AS60A (52-Pin PLCC) MC68HC908AZ60A • MC68HC908AS60A • MC68HC908AS60E Data Sheet, Rev. 6 Freescale Semiconductor Pin Assignments PTD3/ATD11 46 PTD2/ATD10 45 PTD1/ATD9 44 PTD0/ATD8 43 PTB7/ATD7 42 PTB6/ATD6 41 PTB5/ATD5 40 PTB4/ATD4 39 PTB3/ATD3 38 PTB2/ATD2 37 PTB1/ATD1 36 PTB0/ATD0 35 ...

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... MC68HC908AZ60A • MC68HC908AS60A • MC68HC908AS60E Data Sheet, Rev NOTE Chapter 22 Input/Output and MCU 0.1 μ Figure 1-6. Power Supply Bypassing Chapter 19 Serial Peripheral Interface NOTE must be grounded for proper MCU operation. Chapter 17 External Interrupt Module Ports (SPI). Chapter 10 Clock Chapter 9 System (IRQ). Freescale Semiconductor ...

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... Timer Interface Module A (TIMA), and one more of its pins with the Timer Interface Module B (TIMB). See Interface Module B (TIMB), Chapter 26 Analog-to-Digital Converter (ADC) Ports. MC68HC908AZ60A • MC68HC908AS60A • MC68HC908AS60E Data Sheet, Rev. 6 Freescale Semiconductor ) DDA (CGM). ) SSA (CGM). ...

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... Chapter 22 Input/Output and Chapter 22 Input/Output Ports. and Chapter 22 Input/Output Ports. Chapter 23 MSCAN Controller Chapter 23 MSCAN Controller Chapter 27 Byte Data Link Controller Chapter 27 Byte Data Link Controller (SCI), Chapter (TIMA), and Chapter 22 Chapter 25 Timer Interface Module Ports. (MSCAN08). Freescale Semiconductor ...

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... PTE3/TACH1 PTE2/TACH0 PTE1/RxD PTE0/TxD PTF6 PTF5/TBCH1–PTF4/TBCH0 PTF3/TACH5 PTF2/TACH4 PTF1/TACH3 MC68HC908AZ60A • MC68HC908AS60A • MC68HC908AS60E Data Sheet, Rev. 6 Freescale Semiconductor Table 1-1. External Pins Summary Function Driver Type General-Purpose I/O Dual State General-Purpose I/O Dual State ADC Channel General-Purpose I/O Dual State ...

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... N/A N/A N/A N/A N/A N/A No Input Hi-Z N/A N/A Output N/A N/A N/A N/A Input Hi-Z N/A N/A Output Low N/A Yes Input Hi-Z Output No Output N/A Yes Input Hi-Z Output No Output Freescale Semiconductor N/A N/A N/A N/A N/A N/A ...

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... TIMB PIT SIM IRQ BRK LVI CGM MC68HC908AZ60A • MC68HC908AS60A • MC68HC908AS60E Data Sheet, Rev. 6 Freescale Semiconductor Description Buffered version of OSC1 from Clock Generation Module (CGM) PLL-based or OSC1-based clock output from Clock Generator Module (CGM) CGMOUT divided by two SPI serial clock ...

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... Table 1-4. MC Order Numbers Temperature Range –40° 105°C –40° 125°C –40° 105°C –40° 125°C –40° 105°C –40° 125°C Operating –40° 85°C –40° 85°C –40° 85°C Freescale Semiconductor ...

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... MCU operation. • Unimplemented — Accessing an unimplemented location can cause an illegal address reset (within the constraints as outlined in the MC68HC908AZ60A • MC68HC908AS60A • MC68HC908AS60E Data Sheet, Rev. 6 Freescale Semiconductor Chapter 9 System Integration Module Figure 2-1, includes: (SIM)). ...

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... FLASH-1 32,256BYTES SIM BREAK STATUS REGISTER (SBSR) SIM RESET STATUS REGISTER (SRSR) RESERVED Figure 2-1. Memory Map (Sheet MC68HC908AS60A UNIMPLEMENTED 11 BYTES I/O REGISTERS 5 BYTES FLASH-2 432 BYTES Freescale Semiconductor $0000 ↓ $003F $0040 ↓ $004A $004B $004F $0050 ↓ $044F $0450 ↓ ...

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... EEPROM-2 EEDIVH NONVOLATILE REGISTER (EE2DIVHNVR) $FF71 EEPROM-2 EEDIVL NONVOLATILE REGISTER (EE2DIVLNVR) $FF72 $FF73 $FF74 MC68HC908AZ60A • MC68HC908AS60A • MC68HC908AS60E Data Sheet, Rev. 6 Freescale Semiconductor RESERVED RESERVED RESERVED RESERVED FLASH-2 CONTROL REGISTER (FL2CR) RESERVED RESERVED BREAK ADDRESS REGISTER HIGH (BRKH) ...

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... FLASH-2 BLOCK PROTECT REGISTER (FL2BPR) RESERVED 6 BYTES FLASH-1 CONTROL REGISTER (FL1CR) RESERVED RESERVED RESERVED 65 BYTES VECTORS 52 BYTES See Table 2-1 Figure 2-1. Memory Map (Sheet MC68HC908AS60A Freescale Semiconductor $FF75 $FF76 $FF77 $FF78 $FF79 $FF7A $FF7B $FF7C $FF7D $FF7E $FF7F $FF80 $FF81 $FF82 ↓ ...

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... Write: Read: Data Direction Register H $000F (DDRH) Write: Figure 2-2. I/O Data, Status and Control Registers (Sheet MC68HC908AZ60A • MC68HC908AS60A • MC68HC908AS60E Data Sheet, Rev. 6 Freescale Semiconductor Figure 2-2, contain the I/O Data, Status, and Control Registers. Bit PTA7 PTA6 ...

Page 40

... MODFEN SPR1 SPR0 WAKE ILTY PEN PTY TE RE RWU SBK ORIE NEIE FEIE PEIE BKF RPF SCR2 SCR1 SCR0 IRQF 0 IMASK MODE ACK KEYF 0 IMASKK MODEK ACKK VRS7 VRS6 VRS5 VRS4 SSREC COPL STOP COPD 0 PS2 PS1 PS0 Reserved Freescale Semiconductor ...

Page 41

... Control Register (TASC3) Write: Read: Timer A Channel 3 Register $0030 High (TACH3H) Write: Read: Timer A Channel 3 Register $0031 Low (TACH3L) Write: Figure 2-2. I/O Data, Status and Control Registers (Sheet MC68HC908AZ60A • MC68HC908AS60A • MC68HC908AS60E Data Sheet, Rev. 6 Freescale Semiconductor Bit KBIE4 Bit Bit 7 ...

Page 42

... ELS4A TOV4 CH4MAX Bit Bit 0 ELS5B ELS5A TOV5 CH5MAX Bit Bit 0 ADCH3 ADCH2 ADCH1 ADCH0 AD3 AD2 AD1 AD0 BO3 BO2 BO1 BO0 WCM R R TEOD TSIFR TMIFR1 TMIFR0 BD3 BD2 BD1 BD0 0 PS2 PS1 PS0 Bit Bit Reserved Freescale Semiconductor ...

Page 43

... Figure 2-2. I/O Data, Status and Control Registers (Sheet All registers are shown for both MC68HC908AS60A and MC68HC908AZ60A. Refer to individual module chapters to determine if the module is available and the register active or not. MC68HC908AZ60A • MC68HC908AS60A • MC68HC908AS60E Data Sheet, Rev. 6 Freescale Semiconductor Bit ...

Page 44

... UNUSED EEOFF EERAS1 = Unimplemented Bit ILAD 0 LVI HVEN VERF ERASE PGM AT60A R R AZxx Bit Bit EEDIV10 EEDIV9 EEDIV8 EEDIV3 EEDIV2 EEDIV1 EEDIV0 0 EEDIV10 EEDIV9 EEDIV8 EEDIV3 EEDIV2 EEDIV1 EEDIV0 EEBP3 EEBP2 EEBP1 EEBP0 EERAS0 EELAT AUTO EEPGM R = Reserved Freescale Semiconductor ...

Page 45

... Register (FL2BPR) Write: Read: FLASH-1 Control Register $FF88 (FL1CR) Write: Read: COP Control Register $FFFF (COPCTL) Write: Figure 2-3. Additional Status and Control Registers (Sheet MC68HC908AZ60A • MC68HC908AS60A • MC68HC908AS60E Data Sheet, Rev. 6 Freescale Semiconductor Bit UNUSED UNUSED EEPRTCT ECD EEDIV7 EEDIV6 ...

Page 46

... SCI Receive Vector (Low) SCI Error Vector (High) SCI Error Vector (Low) SPI Transmit Vector (High) SPI Transmit Vector (Low) SPI Receive Vector (High) SPI Receive Vector (Low) TIMA Overflow Vector (High) TIMA Overflow Vector (Low) TIMA Channel 5 Vector (High) Freescale Semiconductor ...

Page 47

... Highest Priority $FFFF MC68HC908AZ60A • MC68HC908AS60A • MC68HC908AS60E Data Sheet, Rev. 6 Freescale Semiconductor Vector MC68HC908AZ60A TIMA Overflow Vector (Low) TIMA Channel 5 Vector (Low) TIMA CH3 Vector (High) TIMA Channel 4 Vector (High) TIMA CH3 Vector (Low) TIMA Channel 4 Vector (Low) ...

Page 48

... Memory Map MC68HC908AZ60A • MC68HC908AS60A • MC68HC908AS60E Data Sheet, Rev Freescale Semiconductor ...

Page 49

... During a subroutine call, the CPU uses two bytes of the stack to store the return address. The stack pointer decrements during pushes and increments during pulls. Be careful when using nested subroutines. The CPU could overwrite data in the RAM during a subroutine or during the interrupt stacking operation. MC68HC908AZ60A • MC68HC908AS60A • MC68HC908AS60E Data Sheet, Rev. 6 Freescale Semiconductor NOTE NOTE NOTE 49 ...

Page 50

... Random-Access Memory (RAM) MC68HC908AZ60A • MC68HC908AS60A • MC68HC908AS60E Data Sheet, Rev Freescale Semiconductor ...

Page 51

... Programming tools are available from Freescale. Contact your local Freescale representative for more information. A security feature prevents viewing of the FLASH contents security feature is absolutely secure. However, Freescale’s strategy is to make reading or copying the FLASH difficult for unauthorized users. MC68HC908AZ60A • MC68HC908AS60A • MC68HC908AS60E Data Sheet, Rev. 6 Freescale Semiconductor for details) NOTE (1) 51 ...

Page 52

... This read/write bit configures the memory for program operation. PGM is interlocked with the ERASE bit such that both bits cannot be equal set the same time Program operation selected 0 = Program operation unselected MC68HC908AZ60A • MC68HC908AS60A • MC68HC908AS60E Data Sheet, Rev HVEN Bit 0 MASS ERASE PGM Freescale Semiconductor ...

Page 53

... With this mechanism, the protect start address can be $XX00 and $XX80 (128 byte page boundaries) within the FLASH-1 array. Start address of FLASH block protect Figure 4-3. FLASH-1 Block Protect Start Address FLASH-1 Protected Ranges FL1BPR[7:0] MC68HC908AZ60A • MC68HC908AS60A • MC68HC908AS60E Data Sheet, Rev. 6 Freescale Semiconductor BPR6 BPR5 ...

Page 54

... FL1BPR and the vector locations are erased by either a page or a mass erase operation, both FL1BPR and FL2BPR will also get erased. MC68HC908AZ60A • MC68HC908AS60A • MC68HC908AS60E Data Sheet, Rev NOTE Register. If FL1BPR is programmed with any value other than $FF, NOTE Freescale Semiconductor ...

Page 55

... FLASH array memory space such as the COP Control Register (COPCTL) at $FFFF highly recommended that interrupts be disabled during program/erase operations. MC68HC908AZ60A • MC68HC908AS60A • MC68HC908AS60E Data Sheet, Rev. 6 Freescale Semiconductor NOTE . NOTE FLASH-1 Mass Erase Operation 55 ...

Page 56

... Set the PGM bit in the FLASH-1 Control Register (FL1CR). This configures the memory for program operation and enables the latching of address and data programming. 2. Read the FLASH-1 Block Protect Register (FL1BPR). MC68HC908AZ60A • MC68HC908AS60A • MC68HC908AS60E Data Sheet, Rev NOTE NOTE Freescale Semiconductor ...

Page 57

... This applies particularly to: $FFD2-$FFD3 and $FFDA-$FFFF: Vector area on MC68HC908AS60A (40 bytes) $FFCC-$FFFF: Vector area on MC68HC908AZ60A (52 bytes) MC68HC908AZ60A • MC68HC908AS60A • MC68HC908AS60E Data Sheet, Rev. 6 Freescale Semiconductor Figure NOTE maximum or t maximum. t PROG ...

Page 58

... Set HVEN bit 6 Wait for a time, t pgs 7 Write data to the FLASH address to be programmed 8 Wait for a time, t PROG Completed Y programming this row Clear PGM bit Wait for a time, t nvh Clear HVEN bit Wait for a time, t rcv End of programming Freescale Semiconductor ...

Page 59

... FLASH. Stop mode will suspend any FLASH program/erase operations and leave the memory in a Standby Mode. Standby Mode is the power saving mode of the FLASH module, in which all internal control signals to the FLASH are inactive and the current consumption of the FLASH is minimum. MC68HC908AZ60A • MC68HC908AS60A • MC68HC908AS60E Data Sheet, Rev. 6 Freescale Semiconductor NOTE Low-Power Modes 59 ...

Page 60

... FLASH-1 Memory MC68HC908AZ60A • MC68HC908AS60A • MC68HC908AS60E Data Sheet, Rev Freescale Semiconductor ...

Page 61

... Programming tools are available from Freescale. Contact your local Freescale representative for more information. A security feature prevents viewing of the FLASH contents security feature is absolutely secure. However, Freescale’s strategy is to make reading or copying the FLASH difficult for unauthorized users. MC68HC908AZ60A • MC68HC908AS60A • MC68HC908AS60E Data Sheet, Rev. 6 Freescale Semiconductor NOTE NOTE (1) 61 ...

Page 62

... The FLASH-2 Block Protect Register (FL2BPR) is implemented as a byte within the FLASH-1 memory and therefore can only be written during a FLASH programming sequence. The value in this register determines the starting location of the protected range within the FLASH-2 memory. MC68HC908AZ60A • MC68HC908AS60A • MC68HC908AS60E Data Sheet, Rev HVEN Bit 0 MASS ERASE PGM Freescale Semiconductor ...

Page 63

... With this mechanism, the protect start address can be $XX00 and $XX80 (128 byte page boundaries) within the FLASH-2 array. Start address of FLASH block protect Figure 5-3. FLASH-2 Block Protect Start Address FLASH-2 Protected Ranges: FL2BPR[7:0] MC68HC908AZ60A • MC68HC908AS60A • MC68HC908AS60E Data Sheet, Rev. 6 Freescale Semiconductor BPR6 BPR5 ...

Page 64

... FL1BPR and the vector locations are erased by either a page or a mass erase operation, both FL1BPR and FL2BPR will also get erased. MC68HC908AZ60A • MC68HC908AS60A • MC68HC908AS60E Data Sheet, Rev NOTE Register. If FL2BPR is programmed with any value other than $FF, NOTE Freescale Semiconductor ...

Page 65

... FLASH array memory space such as the COP Control Register (COPCTL) at $FFFF highly recommended that interrupts be disabled during program/erase operations. MC68HC908AZ60A • MC68HC908AS60A • MC68HC908AS60E Data Sheet, Rev. 6 Freescale Semiconductor NOTE . NOTE FLASH-2 Mass Erase Operation 65 ...

Page 66

... Read the FLASH-2 Block Protect Register (FL2BPR). 3. Write to any FLASH-2 address within the row address range desired with any data. MC68HC908AZ60A • MC68HC908AS60A • MC68HC908AS60E Data Sheet, Rev NOTE NOTE Freescale Semiconductor ...

Page 67

... This applies particularly to: $0450-$047F: First row of FLASH-2 (48 bytes) MC68HC908AZ60A • MC68HC908AS60A • MC68HC908AS60E Data Sheet, Rev. 6 Freescale Semiconductor Figure NOTE maximum or t maximum. t ...

Page 68

... Set HVEN bit 6 Wait for a time, t pgs 7 Write data to the FLASH address to be programmed 8 Wait for a time, t PROG Completed Y programming this row Clear PGM bit Wait for a time, t nvh Clear HVEN bit Wait for a time, t rcv End of programming Freescale Semiconductor ...

Page 69

... FLASH. Stop mode will suspend any FLASH program/erase operations and leave the memory in a Standby Mode. Standby Mode is the power saving mode of the FLASH module, in which all internal control signals to the FLASH are inactive and the current consumption of the FLASH is minimum. MC68HC908AZ60A • MC68HC908AS60A • MC68HC908AS60E Data Sheet, Rev. 6 Freescale Semiconductor NOTE Low-Power Modes 69 ...

Page 70

... FLASH-2 Memory MC68HC908AZ60A • MC68HC908AS60A • MC68HC908AS60E Data Sheet, Rev Freescale Semiconductor ...

Page 71

... Nonvolatile EEPROM Configuration and Block Protection Options • On-chip Charge Pump for Programming/Erasing • Security Option • AUTO Bit Driven Programming/Erasing Time Feature 6.3 EEPROM-1 Register Summary The EEPROM-1 Register Summary is shown in MC68HC908AZ60A • MC68HC908AS60A • MC68HC908AS60E Data Sheet, Rev. 6 Freescale Semiconductor Figure 6-1. Chapter 7 71 ...

Page 72

... UNUSED UNUSED EEPRTCT Contents of EE1NVR ($FE1C) = Unimplemented Bit 0 R EEDIV10 EEDIV9 EEDIV8 EEDIV3 EEDIV2 EEDIV1 EEDIV0 0 EEDIV10 EEDIV9 EEDIV8 EEDIV3 EEDIV2 EEDIV1 EEDIV0 EEBP3 EEBP2 EEBP1 EEBP0 EERAS0 EELAT AUTO EEPGM EEBP3 EEBP2 EEBP1 EEBP0 = Reserved UNUSED = Unused Freescale Semiconductor ...

Page 73

... This value is written to the EEPROM-1 Timebase Divider Register (EE1DIVH and EE1DIVL) or programmed into the EEPROM-1 Timebase Divider Nonvolatile Register prior to any EEPROM program or erase operations (6.4.1 EEPROM-1 Configuration MC68HC908AZ60A • MC68HC908AS60A • MC68HC908AS60E Data Sheet, Rev. 6 Freescale Semiconductor -6 +0.5] and 6.4.2 EEPROM-1 Timebase Functional Description Requirements) ...

Page 74

... MC68HC908AZ60A • MC68HC908AS60A • MC68HC908AS60E Data Sheet, Rev and 6.5.2 EEPROM-1 Array Configuration NOTE Address Range EEBP0 $0800–$087F EEBP1 $0880–$08FF EEBP2 $0900–$097F EEBP3 $0980–$09FF 6.5.2 EEPROM-1 Array Configuration Register NOTE Register) Table 6-1 shows the address for Freescale Semiconductor ...

Page 75

... AUTO mode will activate an internal timer that will automatically terminate the program/erase cycle and clear the EEPGM bit. Please see Erasing, and 6.5.1 EEPROM-1 Control Register MC68HC908AZ60A • MC68HC908AS60A • MC68HC908AS60E Data Sheet, Rev. 6 Freescale Semiconductor Description 6.4.5.2 EEPROM-1 for more information. Functional Description Table 6-2 ...

Page 76

... E. Any attempt to clear both EEPGM and EELAT bits with a single instruction will only clear EEPGM. This is to allow time for removal of high voltage from the EEPROM-1 array. MC68HC908AZ60A • MC68HC908AS60A • MC68HC908AS60E Data Sheet, Rev (A) NOTE (B) (D) NOTE Freescale Semiconductor ...

Page 77

... E. Any attempt to clear both EEPGM and EELAT bits with a single instruction will only clear EEPGM. This is to allow time for removal of high voltage from the EEPROM-1 array. MC68HC908AZ60A • MC68HC908AS60A • MC68HC908AS60E Data Sheet, Rev. 6 Freescale Semiconductor NOTE (B) for byte erase; t for block erase ...

Page 78

... Buses configured for EEPROM-1 programming or erase operation 0 = Buses configured for normal operation MC68HC908AZ60A • MC68HC908AS60A • MC68HC908AS60E Data Sheet, Rev EEOFF EERAS1 EERAS0 Unimplemented EERAS1 EERAS0 Bit 0 EELAT AUTO EEPGM MODE Byte Program Byte Erase Block Erase Bulk Erase No Erase/Program Freescale Semiconductor ...

Page 79

... The EEPRTCT bit is used to enable the security feature in the EEPROM (see EEPROM-1 Program/Erase Protection EEPROM-1 security disabled 0 = EEPROM-1 security enabled This feature is a write-once feature. Once the protection is enabled it may not be disabled. MC68HC908AZ60A • MC68HC908AS60A • MC68HC908AS60E Data Sheet, Rev. 6 Freescale Semiconductor Programming, 6.4.5.3 EEPROM-1 NOTE 6 5 ...

Page 80

... Available EEBP3 = 1 Protected EEPRTCT = 0 Byte Programming Available Only Byte Erasing Available Protected Byte Programming Available Only Byte Erasing Available Protected Secured (No Programming or Erasing) Byte Programming Available Only Byte Erasing Available Protected Byte Programming Available Only Byte Erasing Available Protected Freescale Semiconductor ...

Page 81

... EEDIVS- ECD Write: Reset: = Unimplemented Figure 6-5. EE1DIV Divider High Register (EE1DIVH) Address: $FE1B Bit 7 Read: EEDIV7 Write: Reset: Figure 6-6. EE1DIV Divider Low Register (EE1DIVL) MC68HC908AZ60A • MC68HC908AS60A • MC68HC908AS60E Data Sheet, Rev. 6 Freescale Semiconductor UNUSED UNUSED EEPRTCT EEBP3 PV NOTE ...

Page 82

... Reset: Figure 6-8. EEPROM-1 Divider Nonvolatile Register Low (EE1DIVLNVR) MC68HC908AZ60A • MC68HC908AS60A • MC68HC908AS60E Data Sheet, Rev NOTE Unaffected by reset; $FF when blank EEDIV6 EEDIV5 EEDIV4 EEDIV3 Unaffected by reset; $FF when blank +0. Bit 0 EEDIV10 EEDIV9 EEDIV8 2 1 Bit 0 EEDIV2 EEDIV1 EEDIV0 Freescale Semiconductor ...

Page 83

... EEPROM is only possible after the programming sequence has completed. If stop mode is entered while EELAT and EEPGM is cleared, the programming sequence will be terminated abruptly. In either case, the data integrity of the EEPROM is not guaranteed. MC68HC908AZ60A • MC68HC908AS60A • MC68HC908AS60E Data Sheet, Rev. 6 Freescale Semiconductor NOTE Low-Power Modes 83 ...

Page 84

... EEPROM-1 Memory MC68HC908AZ60A • MC68HC908AS60A • MC68HC908AS60E Data Sheet, Rev Freescale Semiconductor ...

Page 85

... Nonvolatile EEPROM Configuration and Block Protection Options • On-chip Charge Pump for Programming/Erasing • Security Option • AUTO Bit Driven Programming/Erasing Time Feature 7.3 EEPROM-2 Register Summary The EEPROM-2 Register Summary is shown in MC68HC908AZ60A • MC68HC908AS60A • MC68HC908AS60E Data Sheet, Rev. 6 Freescale Semiconductor Figure 7-1. Chapter 6 85 ...

Page 86

... UNUSED UNUSED EEPRTCT Contents of EE2NVR ($FF7C) = Unimplemented Bit 0 R EEDIV10 EEDIV9 EEDIV8 EEDIV3 EEDIV2 EEDIV1 EEDIV0 0 EEDIV10 EEDIV9 EEDIV8 EEDIV3 EEDIV2 EEDIV1 EEDIV0 EEBP3 EEBP2 EEBP1 EEBP0 EERAS0 EELAT AUTO EEPGM EEBP3 EEBP2 EEBP1 EEBP0 = Reserved UNUSED = Unused Freescale Semiconductor ...

Page 87

... This value is written to the EEPROM-2 Timebase Divider Register (EE2DIVH and EE2DIVL) or programmed into the EEPROM-2 Timebase Divider Nonvolatile Register prior to any EEPROM program or erase operations (7.4.1 EEPROM-2 Configuration MC68HC908AZ60A • MC68HC908AS60A • MC68HC908AS60E Data Sheet, Rev. 6 Freescale Semiconductor -6 +0.5] and 7.4.2 EEPROM-2 Timebase Functional Description Requirements) ...

Page 88

... MC68HC908AZ60A • MC68HC908AS60A • MC68HC908AS60E Data Sheet, Rev and 7.5.2 EEPROM-2 Array Configuration NOTE Address Range EEBP0 $0600–$067F EEBP1 $0680–$06FF EEBP2 $0700–$077F EEBP3 $0780–$07FF 7.5.2 EEPROM-2 Array Configuration Register NOTE Register) Table 7-1 shows the address for Freescale Semiconductor ...

Page 89

... AUTO mode will activate an internal timer that will automatically terminate the program/erase cycle and clear the EEPGM bit. Please see Erasing, and 7.5.1 EEPROM-2 Control Register MC68HC908AZ60A • MC68HC908AS60A • MC68HC908AS60E Data Sheet, Rev. 6 Freescale Semiconductor Description NOTE 7.4.5.2 EEPROM-2 for more information. ...

Page 90

... E. Any attempt to clear both EEPGM and EELAT bits with a single instruction will only clear EEPGM. This is to allow time for removal of high voltage from the EEPROM-2 array. MC68HC908AZ60A • MC68HC908AS60A • MC68HC908AS60E Data Sheet, Rev (A) NOTE (B) (D) NOTE Freescale Semiconductor ...

Page 91

... E. Any attempt to clear both EEPGM and EELAT bits with a single instruction will only clear EEPGM. This is to allow time for removal of high voltage from the EEPROM-2 array. MC68HC908AZ60A • MC68HC908AS60A • MC68HC908AS60E Data Sheet, Rev. 6 Freescale Semiconductor NOTE (B) for byte erase; t for block erase ...

Page 92

... Buses configured for EEPROM-2 programming or erase operation 0 = Buses configured for normal operation MC68HC908AZ60A • MC68HC908AS60A • MC68HC908AS60E Data Sheet, Rev EEOFF EERAS1 EERAS0 Unimplemented EERAS1 EERAS0 Bit 0 EELAT AUTO EEPGM MODE Byte Program Byte Erase Block Erase Bulk Erase No Erase/Program Freescale Semiconductor ...

Page 93

... The EEPRTCT bit is used to enable the security feature in the EEPROM (see EEPROM-2 Program/Erase Protection EEPROM-2 security disabled 0 = EEPROM-2 security enabled This feature is a write-once feature. Once the protection is enabled it may not be disabled. MC68HC908AZ60A • MC68HC908AS60A • MC68HC908AS60E Data Sheet, Rev. 6 Freescale Semiconductor Programming, 7.4.5.3 EEPROM-2 NOTE 6 5 ...

Page 94

... Available EEBP3 = 1 Protected EEPRTCT = 0 Byte Programming Available Only Byte Erasing Available Protected Byte Programming Available Only Byte Erasing Available Protected Secured (No Programming or Erasing) Byte Programming Available Only Byte Erasing Available Protected Byte Programming Available Only Byte Erasing Available Protected Freescale Semiconductor ...

Page 95

... EEDIVS- ECD Write: Reset: = Unimplemented Figure 7-5. EE2DIV Divider High Register (EE2DIVH) Address: $FF7B Bit 7 Read: EEDIV7 Write: Reset: Figure 7-6. EE2DIV Divider Low Register (EE2DIVL) MC68HC908AZ60A • MC68HC908AS60A • MC68HC908AS60E Data Sheet, Rev. 6 Freescale Semiconductor UNUSED UNUSED EEPRTCT EEBP3 PV NOTE ...

Page 96

... Reset: Figure 7-8. EEPROM-2 Divider Nonvolatile Register Low (EE2DIVLNVR) MC68HC908AZ60A • MC68HC908AS60A • MC68HC908AS60E Data Sheet, Rev NOTE Unaffected by reset; $FF when blank EEDIV6 EEDIV5 EEDIV4 EEDIV3 Unaffected by reset; $FF when blank +0. Bit 0 EEDIV10 EEDIV9 EEDIV8 2 1 Bit 0 EEDIV2 EEDIV1 EEDIV0 Freescale Semiconductor ...

Page 97

... EEPROM is only possible after the programming sequence has completed. If stop mode is entered while EELAT and EEPGM is cleared, the programming sequence will be terminated abruptly. In either case, the data integrity of the EEPROM is not guaranteed. MC68HC908AZ60A • MC68HC908AS60A • MC68HC908AS60E Data Sheet, Rev. 6 Freescale Semiconductor NOTE Low-Power Modes 97 ...

Page 98

... EEPROM-2 Memory MC68HC908AZ60A • MC68HC908AS60A • MC68HC908AS60E Data Sheet, Rev Freescale Semiconductor ...

Page 99

... Modular architecture with expandable internal bus definition for extension of addressing range beyond 64 Kbytes • Low-power stop and wait modes 8.3 CPU Registers Figure 8-1 shows the five CPU registers. CPU registers are not part of the memory map. MC68HC908AZ60A • MC68HC908AS60A • MC68HC908AS60E Data Sheet, Rev. 6 Freescale Semiconductor 99 ...

Page 100

... STACK POINTER (SP) 0 PROGRAM COUNTER (PC CONDITION CODE REGISTER (CCR) CARRY/BORROW FLAG ZERO FLAG NEGATIVE FLAG INTERRUPT MASK HALF-CARRY FLAG TWO’S COMPLEMENT OVERFLOW FLAG Figure 8-1. CPU Registers Unaffected by reset Figure 8-2. Accumulator ( Figure 8-3. Index Register (H: Bit 0 Bit Freescale Semiconductor ...

Page 101

... During reset, the program counter is loaded with the reset vector address located at $FFFE and $FFFF. The vector address is the address of the first instruction to be executed after exiting the reset state. Bit Read: Write: Reset: MC68HC908AZ60A • MC68HC908AS60A • MC68HC908AS60E Data Sheet, Rev. 6 Freescale Semiconductor ...

Page 102

... N — Negative Flag The CPU sets the negative flag when an arithmetic operation, logic operation, or data manipulation produces a negative result, setting bit 7 of the result Negative result 0 = Non-negative result MC68HC908AZ60A • MC68HC908AS60A • MC68HC908AS60E Data Sheet, Rev. 6 102 NOTE 2 1 Bit Freescale Semiconductor ...

Page 103

... CPU instruction, the break interrupt begins immediately. A return-from-interrupt instruction (RTI) in the break routine ends the break interrupt and returns the MCU to normal operation if the break interrupt has been deasserted. MC68HC908AZ60A • MC68HC908AS60A • MC68HC908AS60E Data Sheet, Rev. 6 Freescale Semiconductor Arithmetic/Logic Unit (ALU) 103 ...

Page 104

... EXT IX2 – IX1 SP1 9EE4 ff 4 SP2 9ED4 DIR INH 48 1 INH 58 1 – – IX1 SP1 9E68 ff 5 DIR INH 47 1 INH 57 1 – – IX1 SP1 9E67 DIR (b0 DIR (b1 DIR (b2 DIR (b3 DIR (b4 DIR (b5 DIR (b6 DIR (b7 Freescale Semiconductor ...

Page 105

... CBEQ X+,rel CBEQ opr,SP,rel CLC Clear Carry Bit CLI Clear Interrupt Mask MC68HC908AZ60A • MC68HC908AS60A • MC68HC908AS60E Data Sheet, Rev. 6 Freescale Semiconductor Description ← (PC rel ? ( – – – – – – REL PC ← (PC rel ? IRQ = 1 – – – – – – REL PC ← ...

Page 106

... DIR INH 4A 1 INH 5A 1 – – – IX1 SP1 9E6A ff 5 INH 52 7 IMM DIR EXT IX2 – IX1 SP1 9EE8 ff 4 SP2 9ED8 DIR INH 4C 1 INH 5C 1 – – – IX1 SP1 9E6C ff 5 Freescale Semiconductor ...

Page 107

... ORA opr,SP PSHA Push A onto Stack PSHH Push H onto Stack PSHX Push X onto Stack MC68HC908AZ60A • MC68HC908AS60A • MC68HC908AS60E Data Sheet, Rev. 6 Freescale Semiconductor Effect on CCR Description ← Jump Address – – – – – – PC ← (PC Push (PCL); SP ← (SP) – 1 – ...

Page 108

... IX2 IX1 SP1 9EE2 ff 4 SP2 9ED2 DIR EXT IX2 – IX1 SP1 9EE7 ff 4 SP2 9ED7 – DIR DIR EXT IX2 – IX1 SP1 9EEF ff 4 SP2 9EDF IMM DIR EXT IX2 IX1 SP1 9EE0 ff 4 SP2 9ED0 Freescale Semiconductor ...

Page 109

... Memory location N Negative bit 8.8 Opcode Map See Table 8-2. MC68HC908AZ60A • MC68HC908AS60A • MC68HC908AS60E Data Sheet, Rev. 6 Freescale Semiconductor Description ← (PC Push (PCL) SP ← (SP) – 1; Push (PCH) SP ← (SP) – 1; Push (X) SP ← (SP) – 1; Push (A) – – 1 – – – INH SP ← ...

Page 110

Bit Manipulation Branch Read-Modify-Write DIR DIR REL DIR INH MSB LSB BRSET0 BSET0 BRA NEG NEGA NEGX 3 DIR 2 DIR 2 REL 2 DIR 1 INH 1 5 ...

Page 111

... Master reset control, including power-on reset (POR) and computer operating properly (COP) timeout • Interrupt control: – Acknowledge timing – Arbitration control timing – Vector address generation • CPU enable/disable timing MC68HC908AZ60A • MC68HC908AS60A • MC68HC908AS60E Data Sheet, Rev. 6 Freescale Semiconductor Figure 9-1. Figure 9 summary of the SIM input/output (I/O) 111 ...

Page 112

... SIMOSCEN (TO CGM) COP CLOCK CGMXCLK (FROM CGM) CGMOUT (FROM CGM) INTERNAL CLOCKS LVI (FROM LVI MODULE) ILLEGAL OPCODE (FROM CPU) ILLEGAL ADDRESS (FROM ADDRESS MAP DECODERS) COP (FROM COP MODULE) INTERRUPT SOURCES CPU INTERFACE ILOP ILAD 0 LVI SBFCR $FE03 Freescale Semiconductor Bit ...

Page 113

... In user mode, the internal bus frequency is either the crystal oscillator output (CGMXCLK) divided by four or the PLL output (CGMVCLK) divided by four. (See MC68HC908AZ60A • MC68HC908AS60A • MC68HC908AS60E Data Sheet, Rev. 6 Freescale Semiconductor Table 9-2. Signal Name Conventions Description Buffered Version of OSC1 from Clock Generator Module (CGM) ...

Page 114

... RST IAB PC MC68HC908AZ60A • MC68HC908AS60A • MC68HC908AS60E Data Sheet, Rev. 6 114 9.6.2 Stop 9.4 SIM Counter), but an external reset does not. Each of VECT H Figure 9-4. External Reset Timing Mode. 9.7 SIM Registers). . Figure 9-4 shows the relative timing. RL VECT L Freescale Semiconductor ...

Page 115

... MCU. IRST RST CGMXCLK IAB Reset Recovery Type POR/LVI All others MC68HC908AZ60A • MC68HC908AS60A • MC68HC908AS60E Data Sheet, Rev. 6 Freescale Semiconductor 9-5. RST PULLED LOW BY MCU 32 CYCLES 32 CYCLES Figure 9-5. Internal Reset Timing ILLEGAL ADDRESS RST ILLEGAL OPCODE RST COPRST ...

Page 116

... If the stop enable bit, STOP, in the CONFIG-1 register is logic zero, the SIM treats the STOP instruction as an illegal opcode and causes an illegal opcode reset. MC68HC908AZ60A • MC68HC908AS60A • MC68HC908AS60E Data Sheet, Rev. 6 116 32 32 CYCLES CYCLES Figure 9-7. POR Recovery $FFFE $FFFF Chapter 15 Computer Freescale Semiconductor ...

Page 117

... CGMXCLK cycles down to 32 CGMXCLK cycles. This is ideal for applications using canned oscillators that do not require long start-up times from stop mode. External crystal applications should use the full stop recovery time, that is, with SSREC cleared. MC68HC908AZ60A • MC68HC908AS60A • MC68HC908AS60E Data Sheet, Rev. 6 Freescale Semiconductor WARNING rises above V . Another sixty-four CGMXCLK cycles ...

Page 118

... Active Resets from Internal Sources shows interrupt recovery timing. Figure 9-9. SP – – – – – 1[15: CCR . Figure 9-8 Interrupt Entry for details. The SIM counter is for counter control and Figure 9-8 shows VECT H VECT L START ADDR V DATA H V DATA L OPCODE Freescale Semiconductor ...

Page 119

... YES (AS MANY INTERRUPTS AS EXIST ON CHIP) MC68HC908AZ60A • MC68HC908AS60A • MC68HC908AS60E Data Sheet, Rev. 6 Freescale Semiconductor FROM RESET YES BREAK INTERRUPT? I BIT SET BIT SET? NO YES IRQ1 INTERRUPT? NO STACK CPU REGISTERS. LOAD PC WITH INTERRUPT VECTOR. FETCH NEXT INSTRUCTION. SWI YES INSTRUCTION? NO YES RTI UNSTACK CPU REGISTERS ...

Page 120

... MC68HC908AZ60A • MC68HC908AS60A • MC68HC908AS60E Data Sheet, Rev. 6 120 SP – – – – 1 [7:0] PC – 1 [15:8] Figure 9-10. Interrupt Recovery CLI LDA #$FF PSHH INT1 INTERRUPT SERVICE ROUTINE PULH RTI PSHH INT2 INTERRUPT SERVICE ROUTINE PULH RTI . Interrupt Recognition Example OPCODE OPERAND BACKGROUND ROUTINE Freescale Semiconductor ...

Page 121

... The SIM holds the CPU in a non-clocked state. The operation of each of these modes is described below. Both STOP and WAIT clear the interrupt mask (I) in the condition code register, allowing interrupts to occur. MC68HC908AZ60A • MC68HC908AS60A • MC68HC908AS60E Data Sheet, Rev. 6 Freescale Semiconductor NOTE NOTE (BRK). The SIM puts the CPU into the break state ...

Page 122

... MC68HC908AZ60A • MC68HC908AS60A • MC68HC908AS60E Data Sheet, Rev. 6 122 WAIT ADDR + 1 SAME NEXT OPCODE Figure 9-12. Wait Mode Entry Timing $6E0C $00FF $00FE $A6 $01 $0B $6E RST pin OR CPU interrupt OR break interrupt 32 32 Cycles Cycles $A6 Figure 9-12 SAME SAME SAME $00FD $00FC RST VCT H RST VCT L Freescale Semiconductor ...

Page 123

... NOTE: Previous data can be operand data or the STOP opcode, depending on the last instruction CGMXCLK INT/BREAK IAB STOP +1 Figure 9-16. Stop Mode Recovery from Interrupt or Break MC68HC908AZ60A • MC68HC908AS60A • MC68HC908AS60E Data Sheet, Rev. 6 Freescale Semiconductor NOTE Figure 9-15 NOTE STOP ADDR + 1 PREVIOUS DATA NEXT OPCODE . ...

Page 124

... COP — Computer Operating Properly Reset Bit 1 = Last reset caused by COP counter 0 = POR or read of SRSR MC68HC908AZ60A • MC68HC908AS60A • MC68HC908AS60E Data Sheet, Rev. 6 124 Reserved NOTE: Writing a logic 0 clears PIN COP ILOP ILAD Unimplemented 2 1 Bit See Note Bit 0 0 LVI Freescale Semiconductor ...

Page 125

... This read/write bit enables software to clear status bits by accessing status registers while the MCU break state. To clear status bits during the break state, the BCFE bit must be set Status bits clearable during break 0 = Status bits not clearable during break MC68HC908AZ60A • MC68HC908AS60A • MC68HC908AS60E Data Sheet, Rev. 6 Freescale Semiconductor ...

Page 126

... System Integration Module (SIM) MC68HC908AZ60A • MC68HC908AS60A • MC68HC908AS60E Data Sheet, Rev. 6 126 Freescale Semiconductor ...

Page 127

... Base clock selector circuit — This software-controlled circuit selects either CGMXCLK divided by two or the VCO clock, CGMVCLK, divided by two as the base clock, CGMOUT. The system clocks are derived from CGMOUT. Figure 10-1 shows the structure of the CGM. MC68HC908AZ60A • MC68HC908AS60A • MC68HC908AS60E Data Sheet, Rev. 6 Freescale Semiconductor 127 ...

Page 128

... V SS VRS7–VRS4 VOLTAGE LOOP CONTROLLED FILTER OSCILLATOR PLL ANALOG BANDWIDTH INTERRUPT CONTROL CONTROL AUTO ACQ PLLIE PLLF MUL7–MUL4 CGMVCLK FREQUENCY DIVIDER Figure 10-1. CGM Block Diagram CGMXCLK A CGMOUT ÷ *When CGMOUT = B PTC3 MONITOR MODE USER MODE CGMINT Freescale Semiconductor ...

Page 129

... The PLL is a frequency generator that can operate in either acquisition mode or tracking mode, depending on the accuracy of the output frequency. The PLL can change between acquisition and tracking modes either automatically or manually. MC68HC908AZ60A • MC68HC908AS60A • MC68HC908AS60E Data Sheet, Rev. 6 Freescale Semiconductor Bit ...

Page 130

... MHz) times a linear factor CGMRCLK CGMVCLK Modes. The value of the external capacitor 10.5.2 PLL Bandwidth Control 10.3.3 Base Clock Selector . Modulating the voltage on the is equal to the nominal CGMVRS . NOM , is fed back through /N. 10.3.2.4 CGMVDV CGMVCLK Register. Circuit. The PLL is automatically in Freescale Semiconductor ...

Page 131

... Software must wait a given time, t clock source to CGMOUT (BCS = 1). • The LOCK bit is disabled. • CPU interrupts from the CGM are disabled. MC68HC908AZ60A • MC68HC908AS60A • MC68HC908AS60E Data Sheet, Rev. 6 Freescale Semiconductor Register read-only indicator of the mode of Modes. . See Chapter 28 Electrical unt . See ...

Page 132

... MHz = 32 MHz , equal to the crystal frequency, calculate the VCO frequency RCLK f VCLKDES N = ------------------------- f CGMRCLK 32 MHz N = ------------------- - Example: 4 MHz . CGMVCLK × CGMVCLK CGMRCLK = 8 × 4 MHz = 32 MHz , and compare f with f BUS BUS f CGMVCLK f = ----------------------- - BUS 4 32 MHz f = ------------------- - = Example: BUS BUSDES 8 MHz Freescale Semiconductor or BUSDES ...

Page 133

... VCO clock is selected. The PLL cannot be turned on or off simultaneously with the selection or deselection of the VCO clock. The VCO clock also cannot be selected as the base clock source if the MC68HC908AZ60A • MC68HC908AS60A • MC68HC908AS60E Data Sheet, Rev. 6 Freescale Semiconductor , calculate the VCO linear range multiplier, L. The linear range NOM f ⎛ ...

Page 134

... Refer to manufacturer’s data. S MC68HC908AZ60A • MC68HC908AS60A • MC68HC908AS60E Data Sheet, Rev. 6 134 for routing information and more information on the filter capacitor’s CGMXCLK * Figure 10-3. CGM External Connections Figure 10-3. 10 BYP Freescale Semiconductor ...

Page 135

... CGMXCLK, divided by two or the VCO clock, CGMVCLK, divided by two. 10.4.8 CGM CPU Interrupt (CGMINT) CGMINT is the CPU interrupt signal generated by the PLL lock detector. MC68HC908AZ60A • MC68HC908AS60A • MC68HC908AS60E Data Sheet, Rev. 6 Freescale Semiconductor NOTE should be placed as close to the CGMXFC F connection ...

Page 136

... CGMVCLK, as the source of the CGM output, CGMOUT. CGMOUT frequency is one-half the frequency of the selected clock. BCS cannot be set while the PLLON bit is clear. After toggling BCS, MC68HC908AZ60A • MC68HC908AS60A • MC68HC908AS60E Data Sheet, Rev. 6 136 PLLF 1 PLLON BCS Unimplemented NOTE 2 1 Bit 10.3.3 Base Clock Freescale Semiconductor ...

Page 137

... When the AUTO bit is set, ACQ is a read-only bit that indicates whether the PLL is in acquisition mode or tracking mode. When the AUTO bit is clear, ACQ is a read/write bit that controls whether the PLL is in acquisition or tracking mode. MC68HC908AZ60A • MC68HC908AS60A • MC68HC908AS60E Data Sheet, Rev. 6 Freescale Semiconductor NOTE Circuit. 6 ...

Page 138

... Reset initializes these bits give a default multiply value of 6. MC68HC908AZ60A • MC68HC908AS60A • MC68HC908AS60E Data Sheet, Rev. 6 138 MUL6 MUL5 MUL4 VRS7 10.3.2.4 Programming the PLL). A value the multiplier select bits 2 1 Bit 0 VRS6 VRS5 VRS4 Freescale Semiconductor ...

Page 139

... If the application is not frequency sensitive, CPU interrupt requests should be disabled to prevent PLL interrupt service routines from impeding software performance or from exceeding stack limitations. MC68HC908AZ60A • MC68HC908AS60A • MC68HC908AS60E Data Sheet, Rev. 6 Freescale Semiconductor VCO Frequency Multiplier ( ...

Page 140

... Therefore, the reaction time is constant in this definition, regardless of the size of the step input. For example, consider a system with a 5% acquisition time tolerance command instructs the system to change from MC68HC908AZ60A • MC68HC908AS60A • MC68HC908AS60E Data Sheet, Rev. 6 140 NOTE (BRK). Freescale Semiconductor ...

Page 141

... Noise on the power supply is not acceptable, because it causes small frequency errors which continually change the acquisition time of the PLL. MC68HC908AZ60A • MC68HC908AS60A • MC68HC908AS60E Data Sheet, Rev. 6 Freescale Semiconductor – f des 10.3.2.3 Manual and Automatic PLL Bandwidth , of not more than ± ...

Page 142

... K factor when the PLL is configured in tracking mode. trk Modes). ⎛ V ⎞ ⎛ ⎞ 8 DDA ------------------- - ------------ - t = ⎝ ⎠ ⎝ ⎠ acq f K CGMRDV ACQ ⎛ V ⎞ ⎛ ⎞ 4 DDA ------------------- - ----------- - t = ⎝ ⎠ ⎝ ⎠ CGMRDV TRK Lock ACQ critical F , choose DDA Capacitor). is the K factor when the PLL acq Freescale Semiconductor ...

Page 143

... For example, t ACQ Init. low The filter capacitor should be fully discharged prior to making any measurements. MC68HC908AZ60A • MC68HC908AS60A • MC68HC908AS60E Data Sheet, Rev. 6 Freescale Semiconductor TRK . Therefore, the acquisition time, t Lock , is an integer multiple calculated above. Lock ...

Page 144

... Clock Generator Module (CGM) MC68HC908AZ60A • MC68HC908AS60A • MC68HC908AS60E Data Sheet, Rev. 6 144 Freescale Semiconductor ...

Page 145

... To have the LVI enabled in stop mode, the LVIPWR must logic 1 and the LVISTOP bit must logic 1. Take note that by enabling the LVI in stop mode, the stop I MC68HC908AZ60A • MC68HC908AS60A • MC68HC908AS60E Data Sheet, Rev. 6 Freescale Semiconductor NOTE , and remains at or below that level for at TRIPF ...

Page 146

... MC68HC908AZ60A • MC68HC908AS60A • MC68HC908AS60E Data Sheet, Rev. 6 146 Chapter 16 Low-Voltage Inhibit Chapter 16 Low-Voltage Inhibit 9.6.2 Stop Mode). NOTE Chapter 15 Computer Operating Properly 13 4 – 2 CGMXCLK cycles 18 4 – 2 CGMXCLK cycles Chapter 15 Computer Operating Properly WARNING (LVI)). (LVI)). (COP)). Freescale Semiconductor ...

Page 147

... EExDIV clock input is driven by internal bus clock 0 = EExDIV clock input is driven by CGMXCLK MSCAND — MSCAN Disable Bit MSCAND disables the MSCAN module. (See 1 = MSCAN module disabled 0 = MSCAN Module enabled MC68HC908AZ60A • MC68HC908AS60A • MC68HC908AS60E Data Sheet, Rev. 6 Freescale Semiconductor AT60A R R ...

Page 148

... AZxx — AZxx Emulator Enable Bit AZxx enables the MC68HC08AZxx emulator configuration. This bit will be 0 out of reset MC68HC08AZxx emulator enabled 0 = MC68HC08ASxx emulator enabled AZxx bit is reset by a POWER-ON-RESET only. MC68HC908AZ60A • MC68HC908AS60A • MC68HC908AS60E Data Sheet, Rev. 6 148 NOTE Freescale Semiconductor ...

Page 149

... CPU completes its current instruction. A return-from-interrupt instruction (RTI) in the break routine ends the break interrupt and returns the MCU to normal operation. structure of the break module. MC68HC908AZ60A • MC68HC908AS60A • MC68HC908AS60E Data Sheet, Rev. 6 Freescale Semiconductor Figure 13-1 shows the 149 ...

Page 150

... IAB[15:8] BREAK ADDRESS REGISTER HIGH 8-BIT COMPARATOR 8-BIT COMPARATOR BREAK ADDRESS REGISTER LOW IAB[7:0] Bit Bit Bit BRKE BRKA Unimplemented Figure 13-2. I/O Register Summary Register BRKH BRKL Address $FE0C $FE0D CONTROL BREAK BSCR $FE0E Freescale Semiconductor Bit 0 Bit 8 0 Bit ...

Page 151

... Break address register high (BRKH) • Break address register low (BRKL) • Break status and control register (BSCR) MC68HC908AZ60A • MC68HC908AS60A • MC68HC908AS60E Data Sheet, Rev. 6 Freescale Semiconductor is present on the RST pin. Hi 9.7.1 SIM Break Status Register). Low-Power Modes 151 ...

Page 152

... Register: BRKH Address: $FE0C Bit 7 Read: Bit 15 Write: Reset: 0 Read: Bit 7 Write: Reset: 0 Figure 13-4. Break Address Registers (BRKH and BRKL) MC68HC908AZ60A • MC68HC908AS60A • MC68HC908AS60E Data Sheet, Rev. 6 152 BRKA Unimplemented BRKL $FE0D Bit Bit Bit Bit Freescale Semiconductor ...

Page 153

... All communication between the host computer and the MCU is through the PTA0 pin. A level-shifting and multiplexing interface is required between PTA0 and the host computer. PTA0 is used in a wired-OR configuration and requires a pullup resistor. MC68HC908AZ60A • MC68HC908AS60A • MC68HC908AS60E Data Sheet, Rev. 6 Freescale Semiconductor Figure 14-1 shows a sample 14.3.8 Security) ...

Page 154

... Figure 14-1. Monitor Mode Circuit V DD 68HC08 10 kΩ RST 0.1 μ KΩ IRQ 9.1V CGMXFC 0.022 μF OSC1 * X1 10 MΩ OSC2 V DDA V /V DDA DDAREF 0.1 μF V SSA V SS 0.1 μ kΩ PTA0 PTC3 kΩ 10 kΩ PTC0 A (SEE PTC1 B NOTE.) Freescale Semiconductor ...

Page 155

... Monitor Disabled 1. If the high voltage (V the SIM asserts its COP enable output. The COP is enabled or disabled by the COPD bit in the configuration register. (see MC68HC908AZ60A • MC68HC908AS60A • MC68HC908AS60E Data Sheet, Rev. 6 Freescale Semiconductor Table 14-1. Mode Selection Mode CGMOUT CGMXCLK 1 ...

Page 156

... TWO-STOP-BIT DELAY BEFORE ZERO ECHO Figure 14-5. Break Transaction NEXT START STOP BIT 6 BIT 7 BIT BIT NEXT START STOP BIT 6 BIT 7 BIT BIT STOP NEXT BIT BIT 6 BIT 7 START BIT ADDR. LOW ADDR. LOW DATA RESULT 14-5). When the monitor receives a break Freescale Semiconductor ...

Page 157

... Specifies 2-byte address in high byte:low byte order; low byte followed by data byte Data Returned None Opcode $49 Command Sequence SENT TO MONITOR WRITE WRITE ECHO MC68HC908AZ60A • MC68HC908AS60A • MC68HC908AS60E Data Sheet, Rev. 6 Freescale Semiconductor READ ADDR. HIGH ADDR. HIGH ADDR. HIGH ADDR. HIGH ADDR. LOW Functional Description ADDR. LOW ADDR. LOW DATA RESULT ADDR ...

Page 158

... Reads stack pointer Operand None Data Returned Returns stack pointer in high byte:low byte order Opcode $0C Command Sequence SENT TO MONITOR READSP ECHO MC68HC908AZ60A • MC68HC908AS60A • MC68HC908AS60E Data Sheet, Rev. 6 158 IREAD DATA DATA RESULT IWRITE DATA DATA READSP SP HIGH SP LOW RESULT Freescale Semiconductor ...

Page 159

... PLL programming register (PPG). (See Table 14-9. MC68HC908AS60A Monitor Baud Rate Selection Monitor Baud Rate 4.9152 MHz 4.194 MHz MC68HC908AZ60A • MC68HC908AS60A • MC68HC908AS60E Data Sheet, Rev. 6 Freescale Semiconductor SENT TO MONITOR RUN RUN ECHO Chapter 10 Clock Generator Module VCO Frequency Multiplier (N) ...

Page 160

... WARNING NOTE Error % PTC3=0 PTC3=1 0.64 0.63 900 0.64 0.64 0.64 0.64 0.64 0.64 1.08 1.08 0.49 0.50 0.64 0.64 0.64 0.64 Freescale Semiconductor ...

Page 161

... After receiving the eight security bytes from the host, the MCU transmits a break character signalling that it is ready to receive a command. The MCU does not transmit a break character until after the host sends the eight security bytes. MC68HC908AZ60A • MC68HC908AS60A • MC68HC908AS60E Data Sheet, Rev. 6 Freescale Semiconductor 24 BUS CYCLES (MINIMUM Figure 14-6 ...

Page 162

... Monitor ROM (MON) MC68HC908AZ60A • MC68HC908AS60A • MC68HC908AS60E Data Sheet, Rev. 6 162 Freescale Semiconductor ...

Page 163

... Such an interrupt subroutine could keep the COP from generating a reset even while the main program is not working properly. 15.3 I/O Signals The following paragraphs describe the signals shown in MC68HC908AZ60A • MC68HC908AS60A • MC68HC908AS60E Data Sheet, Rev. 6 Freescale Semiconductor 13 4 – 2 NOTE ...

Page 164

... An internal reset clears the COP prescaler and the COP counter. MC68HC908AZ60A • MC68HC908AS60A • MC68HC908AS60E Data Sheet, Rev. 6 164 12-BIT COP PRESCALER 6-BIT COP COUNTER CLEAR COP COUNTER Figure 15-1. COP Block Diagram 15.4 COP Control RESET RESET STATUS REGISTER Register), clears the COP Freescale Semiconductor ...

Page 165

... The WAIT and STOP instructions put the MCU in low power-consumption standby modes. 15.7.1 Wait Mode The COP remains active in wait mode. To prevent a COP reset during wait mode, periodically clear the COP counter in a CPU interrupt routine. MC68HC908AZ60A • MC68HC908AS60A • MC68HC908AS60E Data Sheet, Rev. 6 Freescale Semiconductor (CONFIG-1)). (CONFIG-1)). 6 5 ...

Page 166

... COP with a STOP instruction, disable the STOP instruction by clearing the STOP bit. 15.8 COP Module During Break Interrupts The COP is disabled during a break interrupt when V MC68HC908AZ60A • MC68HC908AS60A • MC68HC908AS60E Data Sheet, Rev. 6 166 is present on the RST pin. Hi Freescale Semiconductor ...

Page 167

... Operation). The output of the comparator controls the state of the LVIOUT flag in the LVI status register (LVISR). An LVI reset also drives the RST pin low to provide low-voltage protection to external peripheral devices. MC68HC908AZ60A • MC68HC908AS60A • MC68HC908AS60E Data Sheet, Rev. 6 Freescale Semiconductor voltage falls to the LVI trip voltage. DD NOTE ...

Page 168

... DD TRIPF for only one CPU cycle to bring the MCU out of reset. TRIPR FROM CONFIG-1 LVIRST LVI RESET level, software can monitor V level, enabling LVI resets allows the LVI level for nine or more consecutive TRIPF Freescale Semiconductor Bit ...

Page 169

... With the LVIPWR bit in the configuration register programmed to 1, the LVI module is active after a WAIT instruction. With the LVIRST bit in the configuration register programmed to 1, the LVI module can generate a reset and bring the MCU out of wait mode. MC68HC908AZ60A • MC68HC908AS60A • MC68HC908AS60E Data Sheet, Rev. 6 Freescale Semiconductor voltages below the LVI TRIPF 6 5 ...

Page 170

... The LVI feature is intended to provide the safe shutdown of the microcontroller and thus protection of related circuitry prior to any application V DD intended that users operate the microcontroller at lower than specified operating voltage V MC68HC908AZ60A • MC68HC908AS60A • MC68HC908AS60E Data Sheet, Rev. 6 170 NOTE voltage collapsing completely to an unsafe level not . DD Freescale Semiconductor ...

Page 171

... Writing a logic 1 to the ACK bit clears the IRQ latch. • Reset — A reset automatically clears both interrupt latches. MC68HC908AZ60A • MC68HC908AS60A • MC68HC908AS60E Data Sheet, Rev. 6 Freescale Semiconductor Figure 17-1 shows 171 ...

Page 172

... Figure 17-1. IRQ Block Diagram Bit Read Write Reserved R Figure 17-2. IRQ I/O Register Summary NOTE TO CPU FOR BIL/BIH INSTRUCTIONS IRQF SYNCHRO- IRQ NIZER INTERRUPT REQUEST HIGH TO MODE VOLTAGE SELECT DETECT LOGIC IRQF 0 IMASK R R ACK Figure 17-3). Freescale Semiconductor Bit 0 MODE ...

Page 173

... YES MC68HC908AZ60A • MC68HC908AS60A • MC68HC908AS60E Data Sheet, Rev. 6 Freescale Semiconductor FROM RESET I BIT SET? NO YES INTERRUPT? NO STACK CPU REGISTERS. SET I BIT. LOAD PC WITH INTERRUPT VECTOR. FETCH NEXT INSTRUCTION. SWI YES INSTRUCTION? NO RTI YES UNSTACK CPU REGISTERS. INSTRUCTION? NO EXECUTE INSTRUCTION. Figure 17-3. IRQ Interrupt Flowchart ...

Page 174

... To protect the latch during the break state, write a logic 0 to the BCFE bit. With BCFE at logic 0 (its default state), writing to the ACK bit in the IRQ status and control register during the break state has no effect on the IRQ latch. MC68HC908AZ60A • MC68HC908AS60A • MC68HC908AS60E Data Sheet, Rev. 6 174 NOTE 9.7.3 SIM Break Flag Control Register.) Freescale Semiconductor ...

Page 175

... MODE — IRQ Edge/Level Select Bit This read/write bit controls the triggering sensitivity of the IRQ pin. Reset clears MODE IRQ interrupt requests on falling edges and low levels 0 = IRQ interrupt requests on falling edges only MC68HC908AZ60A • MC68HC908AS60A • MC68HC908AS60E Data Sheet, Rev. 6 Freescale Semiconductor ...

Page 176

... External Interrupt Module (IRQ) MC68HC908AZ60A • MC68HC908AS60A • MC68HC908AS60E Data Sheet, Rev. 6 176 Freescale Semiconductor ...

Page 177

... SCI I/O lines are implemented by sharing parallel I/O port pins. The full name of an SCI input or output reflects the name of the shared port pin. SCI I/O pins.The generic pin names appear in the text of this subsection. MC68HC908AZ60A • MC68HC908AS60A • MC68HC908AS60E Data Sheet, Rev. 6 Freescale Semiconductor Table 18-1 shows the full names and the generic names of the 177 ...

Page 178

... ENSCI RPF PRE- BAUD RATE GENERATOR DATA SELECTION ÷ 16 CONTROL Figure 18-1. SCI Module Block Diagram TxD PTE0/SCTxD SCI DATA REGISTER TRANSMIT TxD SHIFT REGISTER TXINV R8 T8 ORIE NEIE FEIE PEIE LOOPS ENSCI TRANSMIT CONTROL M WAKE ILTY PEN PTY Freescale Semiconductor ...

Page 179

... SCI Data Register (SCDR) Write: Reset: Read: SCI Baud Rate Register (SCBR) Write: Reset: Table 18-2. SCI I/O Register Address Summary Register SCC1 Address $0013 MC68HC908AZ60A • MC68HC908AS60A • MC68HC908AS60E Data Sheet, Rev. 6 Freescale Semiconductor Bit LOOPS ENSCI TXINV SCTIE TCIE SCRIE ...

Page 180

... BIT 3 BIT 4 BIT 5 BIT 6 BIT 7 9-BIT DATA FORMAT (BIT M IN SCC1 SET) BIT 2 BIT 3 BIT 4 BIT 5 BIT 6 BIT 7 Figure 18-3. SCI Data Formats Figure 18-3. NEXT START STOP BIT BIT PARITY OR DATA NEXT BIT START BIT 8 STOP BIT BIT Freescale Semiconductor ...

Page 181

... Read: SCI Control Register 2 (SCC2) Write: Reset: Read: SCI Control Register 3 (SCC3) Write: Reset: Figure 18-5. SCI Transmitter I/O Register Summary MC68HC908AZ60A • MC68HC908AS60A • MC68HC908AS60E Data Sheet, Rev. 6 Freescale Semiconductor INTERNAL BUS ÷ 16 SCI DATA REGISTER 11-BIT TRANSMIT SHIFT REGISTER H 8 ...

Page 182

... May set the overrun (OR), noise flag (NF), parity error (PE), or reception in progress flag (RPF) bits MC68HC908AZ60A • MC68HC908AS60A • MC68HC908AS60E Data Sheet, Rev. 6 182 Bit SCTE TC SCRF IDLE Unaffected by Reset 0 0 SCP1 SCP0 Unimplemented U = Unaffected SCC2 SCC3 SCS1 $0014 $0015 $0016 Bit SCR2 SCR1 SCR0 Reserved SCDR SCBR $0018 $0019 Freescale Semiconductor ...

Page 183

... SCDR are empty and that no break or idle character has been generated. The transmission complete interrupt enable bit, TCIE, in SCC2 enables the TC bit to generate transmitter CPU interrupt requests. 18.4.3 Receiver Figure 18-6 shows the structure of the SCI receiver. MC68HC908AZ60A • MC68HC908AS60A • MC68HC908AS60E Data Sheet, Rev. 6 Freescale Semiconductor NOTE NOTE 1.) Functional Description 183 ...

Page 184

... INTERNAL BUS SCR1 SCR2 SCR0 BAUD ÷ 16 DIVIDER DATA H RECOVERY ALL ZEROS WAKEUP LOGIC PARITY CHECKING IDLE ILIE SCRF SCRIE OR ORIE NF NEIE FE FEIE PE PEIE SCI DATA REGISTER 11-BIT RECEIVE SHIFT REGISTER RWU SCRF IDLE R8 ILIE SCRIE OR ORIE NF NEIE FE FEIE PE PEIE Freescale Semiconductor ...

Page 185

... Reset: Read: SCI Baud Rate Register (SCBR) Write: Reset: Figure 18-7. SCI I/O Receiver Register Summary Table 18-4. SCI Receiver I/O Address Summary Register SCC1 Address $0013 MC68HC908AZ60A • MC68HC908AS60A • MC68HC908AS60E Data Sheet, Rev. 6 Freescale Semiconductor Bit LOOPS ENSCI TXINV ...

Page 186

... When the falling edge of a possible start bit occurs, the RT clock begins to count to 16. RxD SAMPLES RT CLOCK RT CLOCK STATE RT CLOCK RESET MC68HC908AZ60A • MC68HC908AS60A • MC68HC908AS60E Data Sheet, Rev. 6 186 START BIT START BIT START BIT DATA QUALIFICATION VERIFICATION SAMPLING Figure 18-8. Receiver Data Sampling LSB Freescale Semiconductor ...

Page 187

... RT8, RT9, and RT10 start bit samples are logic 1s following a successful start bit verification, the noise flag (NF) is set and the receiver assumes that the bit is a start bit. MC68HC908AZ60A • MC68HC908AS60A • MC68HC908AS60E Data Sheet, Rev. 6 Freescale Semiconductor Table 18-5. Start Bit Verification Start Bit Verification Yes ...

Page 188

... The slow stop bit begins at RT8 instead of RT1 but arrives in time for the stop bit data samples at RT8, RT9, and RT10. RECEIVER RT CLOCK MC68HC908AZ60A • MC68HC908AS60A • MC68HC908AS60E Data Sheet, Rev. 6 188 Table 18-7. Stop Bit Recovery Framing Error Flag MSB DATA SAMPLES Figure 18-9. Slow Data Table 18-7 Noise Flag STOP Freescale Semiconductor ...

Page 189

... RT cycles + 10 RT cycles = 170 RT cycles. With the misaligned character shown in when the count of the transmitting device is 11 bit times × cycles = 176 RT cycles. MC68HC908AZ60A • MC68HC908AS60A • MC68HC908AS60E Data Sheet, Rev. 6 Freescale Semiconductor Figure 18-9, the receiver counts 154 RT cycles at the point 154 147 – ...

Page 190

... SCDR, and the new character is lost. The overrun interrupt enable bit, ORIE, in SCC3 enables OR to generate SCI error CPU interrupt requests. MC68HC908AZ60A • MC68HC908AS60A • MC68HC908AS60E Data Sheet, Rev. 6 190 170 176 – × 100 = 3.53%. ------------------------- - 170 NOTE Freescale Semiconductor ...

Page 191

... BCFE is at logic 0. After the break, doing the second step clears the status bit. MC68HC908AZ60A • MC68HC908AS60A • MC68HC908AS60E Data Sheet, Rev. 6 Freescale Semiconductor (BRK)). Low-Power Modes 191 ...

Page 192

... Enables the SCI • Controls output polarity • Controls character length • Controls SCI wakeup method • Controls idle character detection • Enables parity function • Controls parity type MC68HC908AZ60A • MC68HC908AS60A • MC68HC908AS60E Data Sheet, Rev. 6 192 Freescale Semiconductor ...

Page 193

... Beginning the count after the stop bit avoids false idle character recognition, but requires properly synchronized transmissions. Reset clears the ILTY bit Idle character bit count begins after stop bit MC68HC908AZ60A • MC68HC908AS60A • MC68HC908AS60E Data Sheet, Rev. 6 Freescale Semiconductor ...

Page 194

... None 1 9 None 1 7 Even 1 7 Odd 1 8 Even 1 8 Odd 18-8). When enabled, the parity function 18-7). Reset clears the PEN bit. Stop Character Bits Length 1 10 Bits 1 11 Bits 1 10 Bits 1 10 Bits 1 11 Bits 1 11 Bits Freescale Semiconductor ...

Page 195

... Reset clears the TE bit Transmitter enabled 0 = Transmitter disabled Writing to the TE bit is not allowed when the enable SCI bit (ENSCI) is clear. ENSCI is in SCI control register 1. MC68HC908AZ60A • MC68HC908AS60A • MC68HC908AS60E Data Sheet, Rev. 6 Freescale Semiconductor TCIE SCRIE ...

Page 196

... Framing error interrupts – Parity error interrupts Address: $0015 Bit 7 Read: R8 Write: Reset: U Figure 18-13. SCI Control Register 3 (SCC3) MC68HC908AZ60A • MC68HC908AS60A • MC68HC908AS60E Data Sheet, Rev. 6 196 NOTE NOTE ORIE Unimplemented R = Reserved 2 1 Bit 0 NEIE FEIE PEIE Unaffected Freescale Semiconductor ...

Page 197

... Transfer of SCDR data to transmit shift register complete • Transmission complete • Transfer of receive shift register data to SCDR complete • Receiver input idle • Receiver overrun • Noisy data • Framing error • Parity error MC68HC908AZ60A • MC68HC908AS60A • MC68HC908AS60E Data Sheet, Rev. 6 Freescale Semiconductor I/O Registers 197 ...

Page 198

... IDLE bit has been cleared, a valid character must again set the SCRF bit before an idle condition can set the IDLE bit. Reset clears the IDLE bit Receiver input idle 0 = Receiver input active (or idle since the IDLE bit was cleared) MC68HC908AZ60A • MC68HC908AS60A • MC68HC908AS60E Data Sheet, Rev. 6 198 SCRF IDLE Unimplemented 2 1 Bit Freescale Semiconductor ...

Page 199

... CPU interrupt request if the NEIE bit in SCC3 is also set. Clear the NF bit by reading SCS1 and then reading the SCDR. Reset clears the NF bit Noise detected noise detected MC68HC908AZ60A • MC68HC908AS60A • MC68HC908AS60E Data Sheet, Rev. 6 Freescale Semiconductor NORMAL FLAG CLEARING SEQUENCE BYTE 2 BYTE 3 READ SCS1 ...

Page 200

... Polling RPF before disabling the SCI module or entering stop mode can show whether a reception is in progress Reception in progress reception in progress MC68HC908AZ60A • MC68HC908AS60A • MC68HC908AS60E Data Sheet, Rev. 6 200 Unimplemented 2 1 Bit 0 0 BKF RPF Freescale Semiconductor ...

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