MC908AZ60ACFU Freescale Semiconductor, MC908AZ60ACFU Datasheet - Page 342

• Manufacturer Part Number: MC908AZ60ACFU
• Description: IC MCU FLASH 8.4MHZ 60K 64QFP
• Manufacturer: Freescale Semiconductor
• Series: HC08r

Specifications of MC908AZ60ACFU

• Core Processor: HC08
• Core Size: 8-Bit
• Speed: 8.4MHz
• Connectivity: CAN, SCI, SPI
• Peripherals: LVD, POR, PWM
• Number Of I /o: 52
• Program Memory Size: 60KB (60K x 8)
• Program Memory Type: FLASH
• Eeprom Size: 1K x 8
• Ram Size: 2K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 15x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 64-QFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

Byte Data Link Controller (BDLC)
IFR — In-Frame Response Bytes
EOF — End-of-Frame Symbol
IFS — Inter-Frame Separation Symbol
BREAK — Break
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The IFR section of the J1850 message format is optional. Users desiring further definition of in-frame
response should review the SAE J1850 — Class B Data Communications Network Interface
specification.
This symbol is a long 280-μs passive period on the J1850 bus and is longer than an end-of-data (EOD)
symbol, which signifies the end of a message. Since an EOF symbol is longer than a 200-μs EOD
symbol, if no response is transmitted after an EOD symbol, it becomes an EOF, and the message is
assumed to be completed. The EOF flag is set upon receiving the EOF symbol.
The IFS symbol is a 20-μs passive period on the J1850 bus which allows proper synchronization
between nodes during continuous message transmission. The IFS symbol is transmitted by a node
after the completion of the end-of-frame (EOF) period and, therefore, is seen as a 300-μs passive
period.
When the last byte of a message has been transmitted onto the J1850 bus and the EOF symbol time
has expired, all nodes then must wait for the IFS symbol time to expire before transmitting a
start-of-frame (SOF) symbol, marking the beginning of another message.
However, if the BDLC is waiting for the IFS period to expire before beginning a transmission and a
rising edge is detected before the IFS time has expired, it will synchronize internally to that edge. If a
write to the BDR register (for instance, to initiate transmission) occurred on or before 104 • t
the received rising edge, then the BDLC will transmit and arbitrate for the bus. If a CPU write to the
BDR register occurred after 104 • t
transmit, but will wait for the next IFS period to expire before attempting to transmit the byte.
A rising edge may occur during the IFS period because of varying clock tolerances and loading of the
J1850 bus, causing different nodes to observe the completion of the IFS period at different times. To
allow for individual clock tolerances, receivers must synchronize to any SOF occurring during an IFS
period.
The BDLC cannot transmit a BREAK symbol.
If the BDLC is transmitting at the time a BREAK is detected, it treats the BREAK as if a transmission
error had occurred and halts transmission.
If two messages are received with a 300μs (±
(IFS) as measured at the RX pin, the start-of-frame (SOF) symbol of the
second message will generate an invalid symbol interrupt. This interrupt
results in the second message being lost and will therefore be unavailable
to the application software. Implementations of this BDLC design on silicon
have not been exposed to interframe separation rates faster than 320μs in
practical application and have therefore previously not exhibited this
behavior. Ensuring that no nodes on the J1850 network transmit messages
at 300μs (±
developing application software to robustly handle lost messages will
minimize application impact.
MC68HC908AZ60A • MC68HC908AS60A • MC68HC908AS60E Data Sheet, Rev. 6
1
μs) IFS will avoid this missed message frame. In addition,
BDLC
from the detection of the rising edge, then the BDLC will not
NOTE
1
μs) interframe separation
Freescale Semiconductor
BDLC
from