MC908AZ60ACFU Freescale Semiconductor, MC908AZ60ACFU Datasheet - Page 237

• Manufacturer Part Number: MC908AZ60ACFU
• Description: IC MCU FLASH 8.4MHZ 60K 64QFP
• Manufacturer: Freescale Semiconductor
• Series: HC08r

Specifications of MC908AZ60ACFU

• Core Processor: HC08
• Core Size: 8-Bit
• Speed: 8.4MHz
• Connectivity: CAN, SCI, SPI
• Peripherals: LVD, POR, PWM
• Number Of I /o: 52
• Program Memory Size: 60KB (60K x 8)
• Program Memory Type: FLASH
• Eeprom Size: 1K x 8
• Ram Size: 2K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 15x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 64-QFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

PS[2:0] — Prescaler Select Bits
20.8.2 TIMB Counter Registers
The two read-only TIMB counter registers contain the high and low bytes of the value in the TIMB counter.
Reading the high byte (TBCNTH) latches the contents of the low byte (TBCNTL) into a buffer. Subsequent
reads of TBCNTH do not affect the latched TBCNTL value until TBCNTL is read. Reset clears the TIMB
counter registers. Setting the TIMB reset bit (TRST) also clears the TIMB counter registers.
Freescale Semiconductor
These read/write bits select either the PTD4/ATD12/TBCLK pin or one of the seven prescaler outputs
as the input to the TIMB counter as
Register Name and Address
Register Name and Address
If TBCNTH is read during a break interrupt, be sure to unlatch TBCNTL by
reading TBCNTL before exiting the break interrupt. Otherwise, TBCNTL
retains the value latched during the break.
Reset:
Reset:
Read:
Read:
Write:
Write:
MC68HC908AZ60A • MC68HC908AS60A • MC68HC908AS60E Data Sheet, Rev. 6
Figure 20-5. TIMB Counter Registers (TBCNTH and TBCNTL)
BIT 15
BIT 7
Bit 7
Bit 7
0
0
PS[2:0]
= Unimplemented
000
001
010
011
100
101
110
111
BIT 14
BIT 6
6
0
6
0
Table 20-1. Prescaler Selection
Table 20-1
TBCNTH — $0041
TBCNTL — $0042
BIT 13
BIT 5
5
0
5
0
NOTE
BIT 12
Internal Bus Clock ÷ 16
Internal Bus Clock ÷ 32
Internal Bus Clock ÷ 64
BIT 4
shows. Reset clears the PS[2:0] bits.
Internal Bus Clock ÷ 4
Internal Bus Clock ÷ 2
Internal Bus Clock ÷ 8
Internal Bus Clock ÷1
PTD4/ATD12/TBCLK
TIMB Clock Source
4
0
4
0
BIT 11
BIT 3
3
0
3
0
BIT 10
BIT 2
2
0
2
0
BIT 9
BIT 1
1
0
1
0
BIT 0
BIT 8
Bit 0
Bit 0
0
0
I/O Registers
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