MC908AZ60ACFU Freescale Semiconductor, MC908AZ60ACFU Datasheet - Page 123

• Manufacturer Part Number: MC908AZ60ACFU
• Description: IC MCU FLASH 8.4MHZ 60K 64QFP
• Manufacturer: Freescale Semiconductor
• Series: HC08r

Specifications of MC908AZ60ACFU

• Core Processor: HC08
• Core Size: 8-Bit
• Speed: 8.4MHz
• Connectivity: CAN, SCI, SPI
• Peripherals: LVD, POR, PWM
• Number Of I /o: 52
• Program Memory Size: 60KB (60K x 8)
• Program Memory Type: FLASH
• Eeprom Size: 1K x 8
• Ram Size: 2K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 15x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 64-QFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

9.6.2 Stop Mode
In stop mode, the SIM counter is reset and the system clocks are disabled. An interrupt request from a
module can cause an exit from stop mode. Stacking for interrupts begins after the selected stop recovery
time has elapsed. Reset also causes an exit from stop mode.
The SIM disables the clock generator module outputs (CGMOUT and CGMXCLK) in stop mode, stopping
the CPU and peripherals. Stop recovery time is selectable using the SSREC bit in the configuration
register (CONFIG-1). If SSREC is set, stop recovery is reduced from the normal delay of 4096 CGMXCLK
cycles down to 32. This is ideal for applications using canned oscillators that do not require long startup
times from stop mode.
The break module is inactive in Stop mode. The STOP instruction does not affect break module register
states.
The SIM counter is held in reset from the execution of the STOP instruction until the beginning of stop
recovery. It is then used to time the recovery period.
Freescale Semiconductor
CGMXCLK
INT/BREAK
IAB
External crystal applications should use the full stop recovery time by
clearing the SSREC bit.
To minimize stop current, all pins configured as inputs should be driven to
a logic 1 or logic 0.
CPUSTOP
MC68HC908AZ60A • MC68HC908AS60A • MC68HC908AS60E Data Sheet, Rev. 6
NOTE: Previous data can be operand data or the STOP opcode, depending on the last
R/W
IDB
IAB
Figure 9-16. Stop Mode Recovery from Interrupt or Break
instruction
STOP ADDR
STOP +1
.
Figure 9-15. Stop Mode Entry Timing
PREVIOUS DATA
STOP ADDR + 1
STOP + 2
STOP RECOVERY PERIOD
NOTE
NOTE
NEXT OPCODE
Figure 9-15
STOP + 2
SAME
shows stop mode entry timing.
SP
SAME
SP – 1
SAME
SAME
SP – 2
Low-Power Modes
SP – 3
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