M306N5FCTFP Renesas Electronics America, M306N5FCTFP Datasheet - Page 103
![IC M16C MCU FLASH 100QFP](/photos/12/21/122166/qfp100-g1_pkg_sml.jpg)
M306N5FCTFP
Manufacturer Part Number
M306N5FCTFP
Description
IC M16C MCU FLASH 100QFP
Manufacturer
Renesas Electronics America
Series
M16C™ M16C/6Nr
Datasheets
1.M30622SAFPU5.pdf
(308 pages)
2.M306N5FCTFPUK.pdf
(90 pages)
3.M306N5FCTFPU0.pdf
(408 pages)
Specifications of M306N5FCTFP
Core Processor
M16C/60
Core Size
16-Bit
Speed
20MHz
Connectivity
CAN, I²C, IEBus, SIO, UART/USART
Peripherals
DMA, WDT
Number Of I /o
87
Program Memory Size
128KB (128K x 8)
Program Memory Type
FLASH
Ram Size
5K x 8
Voltage - Supply (vcc/vdd)
4.2 V ~ 5.5 V
Data Converters
A/D 26x10b; D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
100-QFP
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
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M16C/6N Group (M16C/6N5)
Rev.2.40
REJ09B0011-0240
Figure 10.9 Hardware Interrupt Priority
10.5.8 Returning from Interrupt Routine
10.5.9 Interrupt Priority
10.5.10 Interrupt Priority Level Select Circuit
The FLG register and PC in the state in which they were immediately before entering the interrupt
sequence are restored from the stack by executing the REIT instruction at the end of the interrupt routine.
Thereafter the CPU returns to the program which was being executed before accepting the interrupt
request.
Return the other registers saved by a program within the interrupt routine using the POPM or similar
instruction before executing the REIT instruction.
Register bank is switched back to the bank used prior to the interrupt sequence by the REIT instruction.
If two or more interrupt requests are sampled at the same sampling points (a timing to detect whether an
interrupt request is generated or not), the interrupt request with the highest priority is acknowledged.
For maskable interrupts (peripheral functions interrupt), any desired priority level can be selected using
bits ILVL2 to ILVL0. However, if two or more maskable interrupts have the same priority level, their
interrupt priority is resolved by hardware, with the highest priority interrupt accepted.
The watchdog timer and other special interrupts have their priority levels set in hardware.
Figure 10.9 shows the Hardware Interrupts Priority.
Software interrupts are not affected by the interrupt priority. If an instruction is executed, control branches
invariably to the interrupt routine.
The interrupt priority level select circuit selects the highest priority interrupt when two or more interrupt
requests are sampled at the same sampling point.
Figure 10.10 shows the Interrupts Priority Select Circuit.
Apr 14, 2006
page 81 of 372
Oscillation stop and re-oscillation detection
Peripheral function
Watchdog timer
Address match
Single step
Reset
DBC
NMI
High
Low
10. Interrupts
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