M306N5FCTFP Renesas Electronics America, M306N5FCTFP Datasheet - Page 154

• Manufacturer Part Number: M306N5FCTFP
• Description: IC M16C MCU FLASH 100QFP
• Manufacturer: Renesas Electronics America
• Series: M16C™ M16C/6Nr

Specifications of M306N5FCTFP

• Core Processor: M16C/60
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: CAN, I²C, IEBus, SIO, UART/USART
• Peripherals: DMA, WDT
• Number Of I /o: 87
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Ram Size: 5K x 8
• Voltage - Supply (vcc/vdd): 4.2 V ~ 5.5 V
• Data Converters: A/D 26x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 100-QFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -

M16C/6N Group (M16C/6N5)
Rev.2.40
REJ09B0011-0240
Figure 14.7 Registers TRGSR and TRBSR
Trigger Select Register
NOTES:
Count Start Flag
b7
b7
1. Set the corresponding port direction bit to 0 (input mode).
2. Overflow or underflow.
Apr 14, 2006
b6
b6
b5
b5
b4
b4
b3
b3
b2
b2
page 132 of 372
b1
b1
b0
b0
TA1TGH
TA2TGH
TA3TGH
TA4TGH
TA1TGL
TA2TGL
TA3TGL
TA4TGL
Symbol
Symbol
TA0S
TA1S
TA2S
TA3S
TA4S
TB0S
TB1S
TB2S
Bit
Bit
TRGSR
TABSR
Symbol
Symbol
Timer A0 count start flag
Timer A1 count start flag
Timer A2 count start flag
Timer A3 count start flag
Timer A4 count start flag
Timer B0 count start flag
Timer B1 count start flag
Timer B2 count start flag
Timer A1 event/trigger
select bits
Timer A2 event/trigger
select bits
Timer A3 event/trigger
select bits
Timer A4 event/trigger
select bits
Bit Name
Bit Name
Address
Address
0383h
0380h
14. Three-Phase Motor Control Timer Function
Set to 01b (TB2 underflow) before
using a V-phase output control circuit
Set to 01b (TB2 underflow) before
using a W-phase output control circuit
b5
Set to 01b (TB2 underflow) before
using a U-phase output control circuit
0 : Count stops
1 : Count starts
0
0
1
1
b4
0
1
0
1
: Input on TA3IN pin is selected
: TB2 is selected
: TA2 is selected
: TA4 is selected
Function
Function
After Reset
After Reset
(2)
(2)
00h
(2)
00h
(1)
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW