M306N5FCTFP Renesas Electronics America, M306N5FCTFP Datasheet - Page 173
![IC M16C MCU FLASH 100QFP](/photos/12/21/122166/qfp100-g1_pkg_sml.jpg)
M306N5FCTFP
Manufacturer Part Number
M306N5FCTFP
Description
IC M16C MCU FLASH 100QFP
Manufacturer
Renesas Electronics America
Series
M16C™ M16C/6Nr
Datasheets
1.M30622SAFPU5.pdf
(308 pages)
2.M306N5FCTFPUK.pdf
(90 pages)
3.M306N5FCTFPU0.pdf
(408 pages)
Specifications of M306N5FCTFP
Core Processor
M16C/60
Core Size
16-Bit
Speed
20MHz
Connectivity
CAN, I²C, IEBus, SIO, UART/USART
Peripherals
DMA, WDT
Number Of I /o
87
Program Memory Size
128KB (128K x 8)
Program Memory Type
FLASH
Ram Size
5K x 8
Voltage - Supply (vcc/vdd)
4.2 V ~ 5.5 V
Data Converters
A/D 26x10b; D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
100-QFP
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
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M16C/6N Group (M16C/6N5)
Rev.2.40
REJ09B0011-0240
Figure 15.13 Transfer Format
15.1.1.4 Continuous Receive Mode
15.1.1.3 LSB First/MSB First Select Function
In continuous receive mode, receive operation becomes enable when the receive buffer register is read.
It is not necessary to write dummy data into the transmit buffer register to enable receive operation in
this mode. However, a dummy read of the receive buffer register is required when starting the operating
mode.
When the UiRRM bit (i = 0 to 2) = 1 (continuous receive mode), the TI bit in the UiC1 register is set to 0
(data present in UiTB register) by reading the UiRB register. In this case, i.e., UiRRM bit = 1, do not write
dummy data to the UiTB register in a program. Bits U0RRM and U1RRM are bits 2 and 3 in the UCON
register, respectively, and the U2RRM bit is the bit 5 in the U2C1 register.
Use the UFORM bit in the UiC0 register (i = 0 to 2) to select the transfer format.
Figure 15.13 shows the Transfer Format.
Apr 14, 2006
(1) When the UFORM bit in the UiC0 register = 0 (LSB first)
(2) When the UFORM bit = 1 (MSB first)
i = 0 to 2
* This applies to the case where the CKPOL bit in the UiC0 register = 0
RXDi
CLKi
TXDi
RXDi
CLKi
TXDi
(transmit data output at the falling edge and the receive data taken in at
the rising edge of the transfer clock) and the UiLCH bit in the UiC1
register = 0 (no reverse).
page 151 of 372
D0
D0
D7
D7
D1
D6
D1
D6
D2
D5
D2
D5
D3
D4
D3
D4
D4
D4
D3
D3
D5
D5
D2
D2
D6
D1
D6
D1
D7
D0
D7
D0
15. Serial Interface
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