M306N5FCTFP Renesas Electronics America, M306N5FCTFP Datasheet - Page 186

• Manufacturer Part Number: M306N5FCTFP
• Description: IC M16C MCU FLASH 100QFP
• Manufacturer: Renesas Electronics America
• Series: M16C™ M16C/6Nr

Specifications of M306N5FCTFP

• Core Processor: M16C/60
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: CAN, I²C, IEBus, SIO, UART/USART
• Peripherals: DMA, WDT
• Number Of I /o: 87
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Ram Size: 5K x 8
• Voltage - Supply (vcc/vdd): 4.2 V ~ 5.5 V
• Data Converters: A/D 26x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 100-QFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -

M16C/6N Group (M16C/6N5)
Rev.2.40
REJ09B0011-0240
Table 15.11 Registers to Be Used and Settings in I
i = 0 to 2
NOTES:
UiTB
UiRB
UiBRG
UiMR
UiC0
UiC1
UiSMR
UiSMR2
UiSMR3
UiSMR4
IFSR0
UCON
Register
1. Not all register bits are described above. Set those bits to 0 when writing to the registers in I
2. Set bits 4 and 5 in registers U0C1 and U1C1 to 0. Bits U0IRS, U1IRS, U0RRM, and U1RRM are in the UCON register.
3.
When using UART1 in I
register to 0 (CTS/RTS function enabled) and the CRS bit to 0 (CTS input).
(1)
(1)
(1)
Apr 14, 2006
0 to 7
0 to 7
8
ABT
OER
0 to 7
SMD2 to SMD0
CKDIR
IOPOL
CLK1 to CLK0
CRS
TXEPT
CRD
NCH
CKPOL
UFORM
TE
TI
RE
RI
U2IRS
U2RRM
UiLCH, UiERE
IICM
ABC
BBS
3 to 7
IICM2
CSC
SWC
ALS
STAC
SWC2
SDHI
7
0, 2, 4, and NODC
CKPH
DL2 to DL0
STAREQ
RSTAREQ
STPREQ
STSPSEL
ACKD
ACKC
SCLHI
SWC9
IFSR06, ISFR07
U0IRS, U1IRS
2 to 7
_______ ________
(3)
(2)
(2)
Bit
page 164 of 372
,
2
C mode and enabling the CTS/RTS separate function of UART0, set the CRD bit in the U1C0
Set transmit data
Receive data can be read
ACK or NACK is set in this bit
Arbitration lost detection flag
Overrun error flag
Set a bit rate
Set to 010b
Set to 0
Set to 0
Select the count source for the UiBRG register
Invalid because the CRD bit = 1
Transmit register empty flag
Set to 1
Set to 1
Set to 0
Set to 1
Set this bit to 1 to enable transmission
Transmit buffer empty flag
Set this bit to 1 to enable reception
Reception complete flag
Invalid
Set to 0
Set to 1
Select the timing at which arbitration-lost
is detected
Bus busy flag
Set to 0
See Table 15.12 I
Set this bit to 1 to enable clock synchronization Set to 0
Set this bit to 1 to have SCLi output fixed to “L” at the falling edge of the 9th bit of clock
Set this bit to 1 to have SDAi output
stopped when arbitration-lost is detected
Set to 0
Set this bit to 1 to have SCLi output forcibly pulled low
Set this bit to 1 to disable SDAi output
Set to 0
Set to 0
See Table 15.12 I
Set the amount of SDAi digital delay
Set this bit to 1 to generate start condition Set to 0
Set this bit to 1 to generate restart condition Set to 0
Set this bit to 1 to generate stop condition Set to 0
Set this bit to 1 to output each condition
Select ACK or NACK
Set this bit to 1 to output ACK data
Set this bit to 1 to have SCLi output
stopped when stop condition is detected
Set to 0
Set to 1
Invalid
Set to 0
Master
2
2
C Mode Functions
C Mode Functions
_______ ________
2
C Mode
_______
Function
Invalid
Invalid
Set to 1
Invalid
Invalid
Set this bit to 1 to initialize UARTi at
start condition detection
Set to 0
Set to 0
Set this bit to 1 to set the SCLi to “L” hold
at the falling edge of the 9th bit of clock
Set to 0
2
C mode.
Slave
15. Serial Interface