M306N5FCTFP Renesas Electronics America, M306N5FCTFP Datasheet - Page 181

• Manufacturer Part Number: M306N5FCTFP
• Description: IC M16C MCU FLASH 100QFP
• Manufacturer: Renesas Electronics America
• Series: M16C™ M16C/6Nr

Specifications of M306N5FCTFP

• Core Processor: M16C/60
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: CAN, I²C, IEBus, SIO, UART/USART
• Peripherals: DMA, WDT
• Number Of I /o: 87
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Ram Size: 5K x 8
• Voltage - Supply (vcc/vdd): 4.2 V ~ 5.5 V
• Data Converters: A/D 26x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 100-QFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -

M16C/6N Group (M16C/6N5)
Rev.2.40
REJ09B0011-0240
Figure 15.19 Transfer Format
15.1.2.2 Counter Measure for Communication Error Occurs
15.1.2.3 LSB First/MSB First Select Function
If a communication error occurs while transmitting or receiving in UART mode, follow the procedures
below.
• Resetting the UiRB register (i = 0 to 2)
• Resetting the UiTB register (i = 0 to 2)
As shown in Figure 15.19, use the UFORM bit in the UiC0 register to select the transfer format.
Figure 15.19 shows the Transfer Format. This function is valid when transfer data is 8-bit long.
Apr 14, 2006
(1) Set the RE bit in the UiC1 register to 0 (reception disabled)
(2) Set the RE bit in the UiC1 register to 1 (reception enabled)
(1) Set bits SMD2 to SMD0 in the UiMR register to 000b (serial interface disabled)
(2) Set bits SMD2 to SMD0 in the UiMR register to 001b, 101b, 110b
(3) 1 (transmission enabled) is written to the TE bit in the UiC1 register, regardless of the TE bit
(2) When the UFORM bit = 1 (MSB first)
(1) When the UFORM bit in the UiC0 register = 0 (LSB first)
i = 0 to 2
ST: Start bit
P: Parity bit
SP: Stop bit
NOTE:
CLKi
TXDi
RXDi
CLKi
TXDi
RXDi
1. This applies to the case where the register bits are set as follows:
CKPOL bit in UiC0 register = 0 (transmit data output at the falling edge and the receive
data taken in at the rising edge of the transfer clock)
UiLCH bit in UiC1 register = 0 (no reverse)
STPS bit in UiMR register = 0 (1 stop bit)
PRYE bit in UiMR register = 1 (parity enabled)
page 159 of 372
ST
ST
ST
ST
D0
D0
D7
D7
D1
D1
D6
D6
D2
D2
D5
D5
D3
D3
D4
D4
D4
D4
D3
D3
D5
D5
D2
D2
D6
D6
D1
D1
D7
D7
D0
D0
P
P
P
P
SP
SP
SP
SP
15. Serial Interface