M306N5FCTFP Renesas Electronics America, M306N5FCTFP Datasheet - Page 213

• Manufacturer Part Number: M306N5FCTFP
• Description: IC M16C MCU FLASH 100QFP
• Manufacturer: Renesas Electronics America
• Series: M16C™ M16C/6Nr

Specifications of M306N5FCTFP

• Core Processor: M16C/60
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: CAN, I²C, IEBus, SIO, UART/USART
• Peripherals: DMA, WDT
• Number Of I /o: 87
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Ram Size: 5K x 8
• Voltage - Supply (vcc/vdd): 4.2 V ~ 5.5 V
• Data Converters: A/D 26x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 100-QFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -

M16C/6N Group (M16C/6N5)
Rev.2.40
REJ09B0011-0240
Figure 16.3 Registers ADCON2, and AD0 to AD7
A/D Control Register 2
NOTES:
A/D Register i (i = 0 to 7)
(b15)
b7
b7
1. If the ADCON2 register is rewritten during A/D conversion, the conversion result will be undefined.
2. The φAD frequency must be 10 MHz or less. The selected φAD frequency is determined by a combination of the
Apr 14, 2006
b6
CKS0 bit in the ADCON0 register, the CKS1 bit in the ADCON1 register, and the CKS2 bit in the ADCON2 register.
CKS2
b5
0
0
0
0
1
1
1
1
b4
b3
0
CKS1
b2
0
0
1
1
0
0
1
1
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b1
(b8)
b0
b0
CKS0
0
1
0
1
0
1
0
1
b7
Bit Symbol
ADGSEL0
ADGSEL1
(1)
(b7-b5)
CKS2
SMP
(b3)
ADCON2
-
-
Divide-by-4 of fAD
Divide-by-2 of fAD
fAD
Divide-by-12 of fAD
Divide-by-6 of fAD
Divide-by-3 of fAD
Symbol
A/D conversion method
select bit
A/D input group select bits
Reserved bit
Frequency select bit 2
Nothing is assigned. If necessary, set to 0.
When read, the content is 0.
Low-order 8 bits of
A/D conversion result
High-order 2 bits of
A/D conversion result
Nothing is assigned. If necessary, set to 0.
When read, the content is 0.
φAD
When BITS bit in ADCON1
register is 1 (10-bit mode)
Bit Name
b0
Address
03D4h
Symbol
AD0
AD1
AD2
AD3
AD4
AD5
AD6
AD7
(2)
b2 b1
0 : Without sample and hold
1 : With sample and hold
0 0 : Port P10 group is selected
0 1 : Do not set a value
1 0 : Port P0 group is selected
1 1 : Port P2 group is selected
Set to 0
0 : Selects fAD, divide-by-2 of fAD, or
1 : Selects divide-by-3 of fAD, divide-by-6
Function
divide-by-4 of fAD.
of fAD, or divide-by-12 of fAD.
After Reset
03C1h to 03C0h
03C3h to 03C2h
03C5h to 03C4h
03C7h to 03C6h
03C9h to 03C8h
03CBh to 03CAh
03CDh to 03CCh
03CFh to 03CEh
A/D conversion result
When read, the content is
undefined.
00h
Address
When BITS bit is 0
Function
(8-bit mode)
After Reset
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
16. A/D Converter
RW
RW
RW
RW
RW
RW
RW
RO
RO
-
-