M306N5FCTFP Renesas Electronics America, M306N5FCTFP Datasheet - Page 198
![IC M16C MCU FLASH 100QFP](/photos/12/21/122166/qfp100-g1_pkg_sml.jpg)
M306N5FCTFP
Manufacturer Part Number
M306N5FCTFP
Description
IC M16C MCU FLASH 100QFP
Manufacturer
Renesas Electronics America
Series
M16C™ M16C/6Nr
Datasheets
1.M30622SAFPU5.pdf
(308 pages)
2.M306N5FCTFPUK.pdf
(90 pages)
3.M306N5FCTFPU0.pdf
(408 pages)
Specifications of M306N5FCTFP
Core Processor
M16C/60
Core Size
16-Bit
Speed
20MHz
Connectivity
CAN, I²C, IEBus, SIO, UART/USART
Peripherals
DMA, WDT
Number Of I /o
87
Program Memory Size
128KB (128K x 8)
Program Memory Type
FLASH
Ram Size
5K x 8
Voltage - Supply (vcc/vdd)
4.2 V ~ 5.5 V
Data Converters
A/D 26x10b; D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
100-QFP
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
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M16C/6N Group (M16C/6N5)
Rev.2.40
REJ09B0011-0240
Table 15.16 Registers to Be Used and Settings in IE Mode
i= 0 to 2
NOTES:
UiTB
UiRB
UiBRG
UiMR
UiC0
UiC1
UiSMR
UiSMR2
UiSMR3
UiSMR4
IFSR0
UCON
15.1.5 Special Mode 3 (IE Mode)
Register
In this mode, one bit of IEBus is approximated with one byte of UART mode waveform.
Table 15.16 lists the Registers to be Used and Settings in IE mode. Figure 15.31 shows the Bus Collision
Detect Function-Related Bits.
If the TXDi pin (i = 0 to 2) output level and RXDi pin input level do not match, a UARTi bus collision detect
interrupt request is generated.
Use bits IFSR06 and IFSR07 in the IFSR0 register to enable the UART0/UART1 bus collision detect function.
1. Not all register bits are described above. Set those bits to 0 when writing to the registers in IE mode.
2. Set bits 4 and 5 in registers U0C1 and U1C1 to 0. Bits U0IRS, U1IRS, U0RRM, and U1RRM are in the
UCON register.
(1)
Apr 14, 2006
0 to 8
0 to 8
OER,FER,PER,SUM
SMD2 to SMD0
CKDIR
STPS
PRY
PRYE
IOPOL
CLK1 to CLK0
CRS
TXEPT
CRD
NCH
CKPOL
UFORM
TE
TI
RE
RI
U2IRS
U2RRM
UiLCH, UiERE
ABSCS
ACSE
SSS
U0IRS, U1IRS
U0RRM, U1RRM
CLKMD0
CLKMD1, RCSP, 7
0 to 7
0 to 3, 7
0 to 7
0 to 7
0 to 7
IFSR06, IFSR07
(2)
(2)
page 176 of 372
Bit
,
Set transmit data
Receive data can be read
Error flag
Set a bit rate
Set to 110b
Select the internal clock or external clock
Set to 0
Invalid because the PRYE bit = 0
Set to 0
Select the TXD/RXD input/output polarity
Select the count source for the UiBRG register
Invalid because the CRD bit = 1
Transmit register empty flag
Set to 1
Select TXDi pin output mode
Set to 0
Set to 0
Set this bit to 1 to enable transmission
Transmit buffer empty flag
Set this bit to 1 to enable reception
Reception complete flag
Select the UART2 transmit interrupt source
Set to 0
Set to 0
Select the sampling timing at which to detect a bus collision
Set this bit to 1 to use the auto clear function of transmit enable bit
Select the transmit start condition
Set to 0
Set to 0
Set to 0
Set to 1
Select the UART0/UART1 transmit interrupt source
Set to 0
Invalid because the CLKMD1 bit = 0
Set to 0
Function
15. Serial Interface
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