M306N5FCTFP Renesas Electronics America, M306N5FCTFP Datasheet - Page 389
![IC M16C MCU FLASH 100QFP](/photos/12/21/122166/qfp100-g1_pkg_sml.jpg)
M306N5FCTFP
Manufacturer Part Number
M306N5FCTFP
Description
IC M16C MCU FLASH 100QFP
Manufacturer
Renesas Electronics America
Series
M16C™ M16C/6Nr
Datasheets
1.M30622SAFPU5.pdf
(308 pages)
2.M306N5FCTFPUK.pdf
(90 pages)
3.M306N5FCTFPU0.pdf
(408 pages)
Specifications of M306N5FCTFP
Core Processor
M16C/60
Core Size
16-Bit
Speed
20MHz
Connectivity
CAN, I²C, IEBus, SIO, UART/USART
Peripherals
DMA, WDT
Number Of I /o
87
Program Memory Size
128KB (128K x 8)
Program Memory Type
FLASH
Ram Size
5K x 8
Voltage - Supply (vcc/vdd)
4.2 V ~ 5.5 V
Data Converters
A/D 26x10b; D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
100-QFP
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
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M16C/6N Group (M16C/6N5)
Rev.2.40
REJ09B0011-0240
23.15.9 Prohibited Instructions
23.15.10 Interrupts
23.15.11 How to Access
23.15.12 Rewriting in User ROM Area
23.15.13 DMA Transfer
The following instructions cannot be used in EW0 mode because the CPU tries to read data in flash
memory: the UND instruction, INTO instruction, JMPS instruction, JSRS instruction, and BRK instruction
EW0 Mode
EW1 Mode
To set the FMR01, FMR02, or FMR11 bit to 1, write 1 after first setting the bit to 0. Do not generate an
interrupt or a DMA transfer between the instruction to set the bit to 0 and the instruction to set the bit to 1.
Set the bit while an “H” signal is applied to the NMI pin.
EW0 Mode
EW1 Mode
In EW1 mode, do not perform a DMA transfer while the FMR00 bit in the FMR0 register is set to 0 (auto-
programming or auto-erasure).
• The NMI and watchdog timer interrupts are available since registers FMR0 and FMR1 are forcibly reset
• The address match interrupt is not available since the CPU tries to read data in the flash memory.
• Do not acknowledge any interrupts with vectors in the relocatable vector table or address match interrupt
• Do not use the watchdog timer interrupt.
• The NMI interrupt is available since registers FMR0 and FMR1 are forcibly reset when the interrupt
If the supply voltage drops while rewriting the block where the rewrite control program is stored, the flash
memory cannot be rewritten because the rewrite control program is not correctly rewritten. If this error
occurs, rewrite the user ROM area while in standard serial I/O mode, parallel I/O mode, or CAN I/O
mode.
Avoid rewriting any block in which the rewrite control program is stored.
To use interrupts having vectors in a relocatable vector table, the vectors must be relocated to the RAM
area.
when either interrupt request is generated. Allocate the jump addresses for each interrupt service
routines to the fixed vector table. Flash memory rewrite operation is suspended when the NMI or
watchdog timer interrupt request is generated. Execute the rewrite program again after exiting the
interrupt routine.
during auto-programming or auto-erasure.
request is generated. Allocate the jump address for the interrupt service routine to the fixed vector table.
Flash memory rewrite operation is suspended when the NMI interrupt request is generated. Execute the
rewrite program again after exiting the interrupt service routine.
Apr 14, 2006
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page 367 of 372
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23. Usage Notes
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