M306N5FCTFP Renesas Electronics America, M306N5FCTFP Datasheet - Page 397

• Manufacturer Part Number: M306N5FCTFP
• Description: IC M16C MCU FLASH 100QFP
• Manufacturer: Renesas Electronics America
• Series: M16C™ M16C/6Nr

Specifications of M306N5FCTFP

• Core Processor: M16C/60
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: CAN, I²C, IEBus, SIO, UART/USART
• Peripherals: DMA, WDT
• Number Of I /o: 87
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Ram Size: 5K x 8
• Voltage - Supply (vcc/vdd): 4.2 V ~ 5.5 V
• Data Converters: A/D 26x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 100-QFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -

2.00 Nov. 10, 2004
Rev.
Date
REVISION HISTORY
Page
103
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66
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83
86
Figure 8.13 State Transition in Normal Operation Mode
Figure 8.14 Procedure to Switch Clock Source from On-chip Oscillator to Main Clock
is revised.
Table 10.2 Relocatable Vector Tables
Figure 10.3 Interrupt Control Registers (1): NOTE 5 is added.
Figure 10.4 Interrupt Control Registers (2)
10.9 CAN0 Wake-up Interrupt is revised.
Figure 10.13 CAN0 Wake-up Interrupt Block Diagram is revised.
Figure 11.1 Watchdog Timer Block Diagram: "RESET" is revised to "Internal RESET signal".
Figure 13.6 (upper and middle) ONSF Register, TRGSR Register: NOTE 2 is added.
Table 13.1 Specifications in Timer Mode
Table 13.2 Specifications in Event Counter Mode (when not processing two-phase pulse signal)
13.1.2.1 Counter Initialization by Two-Phase Pulse Signal Processing 4th line
Figure 13.10 Two-phase Pulse (A phase and B phase) and Z Phase
Figure 13.12 TA0MR to TA4MR Registers in PWM Mode
Table 13.6 Specifications in Timer Mode
Figure 14.1 Three-Phase Motor Control Timer Function Block Diagram is revised.
Figure 14.2 INVC0 Register is revised.
Figure 14.3 INVC1 Register: Function of INV13 bit is revised.
Figure 14.4 (upper) IDB0 and IDB1 Registers: (b7-b6) is revised.
Figure 14.4 (lower) DTT Register: NOTE 2 is revised.
Figure 14.6 (upper) ICTB2 Register
Figure 14.7 (upper) TRGSR Register: NOTE 2 is added.
Figure 14.8 (upper) TA1MR, TA2MR and TA4MR Registers
• Low-Speed and Low Power Dissipation Mode: "CM7 = 1” is revised to "CM7 = 0" (3 places).
• NOTES 2, 6 are revised.
• Interrupt Source: "Software interrupt" is revised to "INT Instruction Interrupt"
• NOTE 2 is added to INT5IC, S3IC/INT4IC
• NOTE 6 is added.
• Specification of Divide Ratio: "TAiMR register" is revised to "TAi register".
• Specification of Select Function: "When not counting, the pin outputs a low" is
• Specification in Select Function: "When not counting, the pin outputs a low" is
•
•
• Bit name and Function in MR0 bit is revised from "Set to "1" in PWM mode" to "Pulse
• NOTE 3 is added.
• Specification in Divide Ratio: "TBiMR register" is revised to "TBi register".
• (b7-b4) is revised.
• NOTE 3 is added.
• Function of MR1 bit: "Has no effect" is revised to "Set to "0" ".
revised to "When TAiS bit is set to "0" (stop counting), the pin outputs a low".
revised to "When TAiS bit is set to "0" (stop counting), the pin outputs a low".
"the INT2 pin" is revised to "the ZP pin".
"INT2 (Z phase)" is revised to "ZP".
Output Function Select Bit
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M16C/6N Group (M16C/6N5) Hardware Manual
C-3
(3)
Description
".
Summary
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