MFRC52301HN1,151 NXP Semiconductors, MFRC52301HN1,151 Datasheet - Page 45

• Manufacturer Part Number: MFRC52301HN1,151
• Description: IC MIFARE READER 32-HVQFN
• Manufacturer: NXP Semiconductors
• Series: MIFARE®r

Specifications of MFRC52301HN1,151

• Frequency: 13.56MHz
• Package / Case: 32-VQFN Exposed Pad, 32-HVQFN, 32-SQFN, 32-DHVQFN
• Operating Current: 7 mA
• Operating Voltage: 2.5 V to 3.6 V
• Product: RFID Readers
• Wireless Frequency: 13.56 MHz
• Interface Type: RS-232, I2C
• Data Rate: 100 Kbps
• Operating Temperature Range: - 25 C to +85 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -
• Rf Type: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 568-4766; 935282956151; MFRC52301HN1

NXP Semiconductors
MFRC523_32
Product data sheet
PUBLIC
9.2.1.14 BitFramingReg register
9.2.1.15 CollReg register
Adjustments for bit-oriented frames.
Table 47.
Table 48.
Defines the first bit-collision detected on the RF interface.
Table 49.
Table 50.
Bit
Symbol
Access
Bit
7
6 to 4
3
2 to 0
Bit
Symbol
Access
Bit
7
6
5
Symbol
ValuesAfterColl
reserved
CollPosNotValid
StartSend
Symbol
StartSend
RxAlign[2:0]
reserved
TxLastBits[2:0]
ValuesAfterColl reserved
BitFramingReg register (address 0Dh); reset value: 00h bit allocation
BitFramingReg register bit descriptions
CollReg register (address 0Eh); reset value: xxh bit allocation
CollReg register bit descriptions
W
7
R/W
7
Rev. 3.2 — 12 January 2010
6
Value Description
1
0
1
7
-
-
RxAlign[2:0]
6
-
115232
starts the transmission of data
only valid in combination with the Transceive command
used for reception of bit-oriented frames: defines the bit
position for the first bit received to be stored in the FIFO buffer
example:
These bits are only to be used for bitwise anticollision at
106 kBd, for all other modes they are set to 0
reserved for future use
used for transmission of bit oriented frames: defines the
number of bits of the last byte that will be transmitted
000b indicates that all bits of the last byte will be transmitted
-
1
Value Description
0
R/W
5
LSB of the received bit is stored at bit position 0, the second
received bit is stored at bit position 1
LSB of the received bit is stored at bit position 1, the second
received bit is stored at bit position 2
LSB of the received bit is stored at bit position 7, the second
received bit is stored in the next byte that follows at bit
position 0
CollPosNotValid
all received bits will be cleared after a collision
only used during bitwise anticollision at 106 kBd,
otherwise it is set to logic 1
reserved for future use
no collision detected or the position of the collision is
out of the range of CollPos[4:0]
R
5
4
reserved
3
-
4
3
2
CollPos[4:0]
Contactless reader IC
TxLastBits[2:0]
MFRC523
R
2
© NXP B.V. 2010. All rights reserved.
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0
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