MFRC52301HN1,151 NXP Semiconductors, MFRC52301HN1,151 Datasheet - Page 52

• Manufacturer Part Number: MFRC52301HN1,151
• Description: IC MIFARE READER 32-HVQFN
• Manufacturer: NXP Semiconductors
• Series: MIFARE®r

Specifications of MFRC52301HN1,151

• Frequency: 13.56MHz
• Package / Case: 32-VQFN Exposed Pad, 32-HVQFN, 32-SQFN, 32-DHVQFN
• Operating Current: 7 mA
• Operating Voltage: 2.5 V to 3.6 V
• Product: RFID Readers
• Wireless Frequency: 13.56 MHz
• Interface Type: RS-232, I2C
• Data Rate: 100 Kbps
• Operating Temperature Range: - 25 C to +85 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -
• Rf Type: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 568-4766; 935282956151; MFRC52301HN1

NXP Semiconductors
MFRC523_32
Product data sheet
PUBLIC
9.2.2.10 DemodReg register
9.2.2.11 Reserved register 1Ah
9.2.2.9 RxThresholdReg register
Selects thresholds for the bit decoder.
Table 69.
Table 70.
Defines demodulator settings.
Table 71.
Table 72.
Functionality is reserved for future use.
Bit
Symbol
Access
Bit
7 to 4
3
2 to 0
Bit
Symbol
Access
Bit
7 to 6
5
4
3 to 2
1 to 0
Symbol
AddIQ
[1:0]
FixIQ
reserved
TauRcv
[1:0]
TauSync
[1:0]
Symbol
MinLevel
[3:0]
reserved
CollLevel
[2:0]
RxThresholdReg register (address 18h); reset value: 84h bit allocation
RxThresholdReg register bit descriptions
DemodReg register (address 19h); reset value: 4Dh bit allocation
DemodReg register bit descriptions
7
7
AddIQ[1:0]
R/W
Value
-
00
01
10
11
1
-
-
-
Rev. 3.2 — 12 January 2010
MinLevel[3:0]
Description
defines the minimum signal strength at the decoder input that will be
accepted
if the signal strength is below this level it is not evaluated
reserved for future use
defines the minimum signal strength at the decoder input that must be
reached by the weaker half-bit of the Manchester encoded signal to
generate a bit-collision relative to the amplitude of the stronger half-bit
6
6
Description
defines the use of I and Q channel during reception
Remark: the FixIQ bit must be set to logic 0 to enable the following
settings:
if AddIQ[1:0] are set to X0b, the reception is fixed to I channel
if AddIQ[1:0] are set to X1b, the reception is fixed to Q channel
reserved for future use
changes the time-constant of the internal PLL during data reception
Remark: if set to 00b the PLL is frozen during data reception
changes the time constant of the internal PLL during burst
R/W
selects the stronger channel
selects the stronger channel and freezes the selected channel
during communication
reserved
reserved
115232
FixIQ
R/W
5
5
reserved
4
4
-
reserved
3
3
-
TauRcv[1:0]
R/W
2
2
Contactless reader IC
CollLevel[2:0]
MFRC523
© NXP B.V. 2010. All rights reserved.
R/W
TauSync[1:0]
1
1
R/W
52 of 98
0
0