MFRC52301HN1,151 NXP Semiconductors, MFRC52301HN1,151 Datasheet - Page 94

• Manufacturer Part Number: MFRC52301HN1,151
• Description: IC MIFARE READER 32-HVQFN
• Manufacturer: NXP Semiconductors
• Series: MIFARE®r

Specifications of MFRC52301HN1,151

• Frequency: 13.56MHz
• Package / Case: 32-VQFN Exposed Pad, 32-HVQFN, 32-SQFN, 32-DHVQFN
• Operating Current: 7 mA
• Operating Voltage: 2.5 V to 3.6 V
• Product: RFID Readers
• Wireless Frequency: 13.56 MHz
• Interface Type: RS-232, I2C
• Data Rate: 100 Kbps
• Operating Temperature Range: - 25 C to +85 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -
• Rf Type: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 568-4766; 935282956151; MFRC52301HN1

NXP Semiconductors
Table 68. RxSelReg register bit descriptions . . . . . . . . . .51
Table 69. RxThresholdReg register (address 18h);
Table 70. RxThresholdReg register bit descriptions . . . .52
Table 71. DemodReg register (address 19h);
Table 72. DemodReg register bit descriptions . . . . . . . . .52
Table 73. Reserved register (address 1Ah);
Table 74. Reserved register bit descriptions . . . . . . . . . .53
Table 75. Reserved register (address 1Bh);
Table 76. Reserved register bit descriptions . . . . . . . . . .53
Table 77. MfTxReg register (address 1Ch);
Table 78. MfTxReg register bit descriptions . . . . . . . . . .53
Table 79. MfRxReg register (address 1Dh);
Table 80. MfRxReg register bit descriptions . . . . . . . . . .54
Table 81. TypeBReg register (address 1Eh);
Table 82. TypeBReg register bit descriptions . . . . . . . . .54
Table 83. SerialSpeedReg register (address 1Fh);
Table 84. SerialSpeedReg register bit descriptions . . . .55
Table 85. Reserved register (address 20h);
Table 86. Reserved register bit descriptions . . . . . . . . . .56
Table 87. CRCResultReg (higher bits) register
Table 88. CRCResultReg register higher
Table 89. CRCResultReg (lower bits) register
Table 90. CRCResultReg register lower
Table 91. Reserved register (address 23h);
Table 92. Reserved register bit descriptions . . . . . . . . . .57
Table 93. ModWidthReg register (address 24h);
Table 94. ModWidthReg register bit descriptions . . . . . .57
Table 95. Reserved register (address 25h);
Table 96. Reserved register bit descriptions . . . . . . . . . .57
Table 97. RFCfgReg register (address 26h);
Table 98. RFCfgReg register bit descriptions . . . . . . . . .58
Table 99. GsNReg register (address 27h);
MFRC523_32
Product data sheet
PUBLIC
reset value: 84h bit allocation . . . . . . . . . . . . .52
reset value: 4Dh bit allocation . . . . . . . . . . . . .52
reset value: 00h bit allocation . . . . . . . . . . . . .53
reset value: 00h bit allocation . . . . . . . . . . . . .53
reset value: 62h bit allocation . . . . . . . . . . . . .53
reset value: 00h bit allocation . . . . . . . . . . . . .54
reset value: 00h bit allocation . . . . . . . . . . . . .54
reset value: EBh bit allocation . . . . . . . . . . . . .55
reset value: 00h bit allocation . . . . . . . . . . . . .56
(address 21h); reset value:
FFh bit allocation . . . . . . . . . . . . . . . . . . . . . . .56
bit descriptions . . . . . . . . . . . . . . . . . . . . . . . . .56
(address 22h); reset value:
FFh bit allocation . . . . . . . . . . . . . . . . . . . . . . .56
bit descriptions . . . . . . . . . . . . . . . . . . . . . . . . .56
reset value: 88h bit allocation . . . . . . . . . . . . .57
reset value: 26h bit allocation . . . . . . . . . . . . .57
reset value: 87h bit allocation . . . . . . . . . . . . .57
reset value: 48h bit allocation . . . . . . . . . . . . .58
Rev. 3.2 — 12 January 2010
115232
Table 100.GsNReg register bit descriptions . . . . . . . . . . 58
Table 101.CWGsPReg register (address 28h);
Table 102.CWGsPReg register bit descriptions . . . . . . . . 59
Table 103.ModGsPReg register (address 29h);
Table 104.ModGsPReg register bit descriptions . . . . . . . 59
Table 105.TModeReg register (address 2Ah);
Table 106.TModeReg register bit descriptions . . . . . . . . 60
Table 107.TPrescalerReg register (address 2Bh);
Table 108.TPrescalerReg register bit descriptions . . . . . 60
Table 109.TReloadReg (higher bits) register
Table 110.TReloadReg register higher
Table 111.TReloadReg (lower bits) register
Table 112.TReloadReg register lower
Table 113.TCounterValReg (higher bits) register
Table 114.TCounterValReg register higher
Table 115.TCounterValReg (lower bits) register
Table 116.TCounterValReg register lower
Table 117.Reserved register (address 30h);
Table 118.Reserved register bit descriptions . . . . . . . . . . 62
Table 119.TestSel1Reg register (address 31h);
Table 120.TestSel1Reg register bit descriptions . . . . . . . 62
Table 121.TestSel2Reg register (address 32h);
Table 122.TestSel2Reg register bit descriptions . . . . . . . 63
Table 123.TestPinEnReg register (address 33h);
Table 124.TestPinEnReg register bit descriptions . . . . . . 63
Table 125.TestPinValueReg register (address 34h);
Table 126.TestPinValueReg register bit descriptions . . . . 64
Table 127.TestBusReg register (address 35h);
reset value: 88h bit allocation . . . . . . . . . . . . . 58
reset value: 20h bit allocation . . . . . . . . . . . . . 59
reset value: 20h bit allocation . . . . . . . . . . . . . 59
reset value: 00h bit allocation . . . . . . . . . . . . . 59
reset value: 00h bit allocation . . . . . . . . . . . . . 60
(address 2Ch); reset value:
00h bit allocation . . . . . . . . . . . . . . . . . . . . . . . 61
bit descriptions . . . . . . . . . . . . . . . . . . . . . . . . 61
(address 2Dh); reset value:
00h bit allocation . . . . . . . . . . . . . . . . . . . . . . . 61
bit descriptions . . . . . . . . . . . . . . . . . . . . . . . . 61
(address 2Eh); reset value:
xxh bit allocation . . . . . . . . . . . . . . . . . . . . . . . 61
bit descriptions . . . . . . . . . . . . . . . . . . . . . . . . 61
(address 2Fh); reset value:
xxh bit allocation . . . . . . . . . . . . . . . . . . . . . . . 61
bit descriptions . . . . . . . . . . . . . . . . . . . . . . . . 62
reset value: 00h bit allocation . . . . . . . . . . . . . 62
reset value: 00h bit allocation . . . . . . . . . . . . . 62
reset value: 00h bit allocation . . . . . . . . . . . . . 62
reset value: 80h bit allocation . . . . . . . . . . . . . 63
reset value: 00h bit allocation . . . . . . . . . . . . . 63
reset value: xxh bit allocation . . . . . . . . . . . . . 64
Contactless reader IC
MFRC523
© NXP B.V. 2010. All rights reserved.
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