MFRC52301HN1,151 NXP Semiconductors, MFRC52301HN1,151 Datasheet - Page 40

• Manufacturer Part Number: MFRC52301HN1,151
• Description: IC MIFARE READER 32-HVQFN
• Manufacturer: NXP Semiconductors
• Series: MIFARE®r

Specifications of MFRC52301HN1,151

• Frequency: 13.56MHz
• Package / Case: 32-VQFN Exposed Pad, 32-HVQFN, 32-SQFN, 32-DHVQFN
• Operating Current: 7 mA
• Operating Voltage: 2.5 V to 3.6 V
• Product: RFID Readers
• Wireless Frequency: 13.56 MHz
• Interface Type: RS-232, I2C
• Data Rate: 100 Kbps
• Operating Temperature Range: - 25 C to +85 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -
• Rf Type: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 568-4766; 935282956151; MFRC52301HN1

NXP Semiconductors
MFRC523_32
Product data sheet
PUBLIC
9.2.1.7 ErrorReg register
Error bit register showing the error status of the last command executed.
Table 33.
Table 34:
[1]
Bit Symbol
7
6
5
4
3
2
1
0
Bit
Symbol
Access
Command execution clears all error bits except the TempErr bit. Cannot be set by software.
WrErr
TempErr
reserved
BufferOvfl
CollErr
CRCErr
ParityErr
ProtocolErr 1
WrErr
ErrorReg register (address 06h); reset value: 00h bit allocation
ErrorReg register bit descriptions
R
[1]
7
Value Description
1
1
-
1
1
1
1
TempErr
R
6
Rev. 3.2 — 12 January 2010
data is written into the FIFO buffer by the host during the MFAuthent
command or if data is written into the FIFO buffer by the host during the
time between sending the last bit on the RF interface and receiving the
last bit on the RF interface
internal temperature sensor detects overheating, in which case the
antenna drivers are automatically switched off
reserved for future use
the host or a MFRC523’s internal state machine (e.g. receiver) tries to
write data to the FIFO buffer even though it is already full
a bit-collision is detected
cleared automatically at receiver start-up phase
only valid during the bitwise anticollision at 106 kBd
always set to logic 0 during communication protocols at 212 kBd,
424 kBd and 848 kBd
the RxModeReg register’s RxCRCEn bit is set and the CRC calculation
fails
automatically cleared to logic 0 during receiver start-up phase
parity check failed
automatically cleared during receiver start-up phase
only valid for ISO/IEC 14443 A/MIFARE communication at 106 kBd
set to logic 1 if the SOF is incorrect
automatically cleared during receiver start-up phase
bit is only valid for 106 kBd
during the MFAuthent command, the ProtocolErr bit is set to logic 1 if the
number of bytes received in one data stream is incorrect
reserved
115232
5
-
BufferOvfl
R
4
CollErr
R
3
CRCErr
R
2
Contactless reader IC
ParityErr
MFRC523
© NXP B.V. 2010. All rights reserved.
R
1
ProtocolErr
R
0
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