XR17V258IV-F Exar Corporation, XR17V258IV-F Datasheet
XR17V258IV-F
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XR17V258IV-F Summary of contents
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PCI BUS OCTAL UART WITH POWER MANAGEMENT SUPPORT AUGUST 2010 GENERAL DESCRIPTION 1 The XR17V258 (V258 single chip 8-channel 66MHz PCI (Peripheral Component Interconnect) UART (Universal Asynchronous Transmitter) solution, optimized performance and lower power. The V258 device ...
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... GND 137 VCC 138 AD31 139 AD30 140 AD29 AD28 141 AD27 142 AD26 143 144 AD25 ORDERING INFORMATION ART UMBER ACKAGE XR17V258IV 144-Lead LQFP XR17V258 PERATING EMPERATURE ANGE -40°C to +85°C 2 REV. 1.0.2 72 CTS5# 71 RX5 ENIR 70 69 TMRCK 68 MPIO4 67 MPIO5 ...
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PCI BUS OCTAL UART WITH POWER MANAGEMENT SUPPORT REV. 1.0.2 PIN DESCRIPTIONS AME IN YPE PCI LOCAL BUS INTERFACE RST# 134 CLK 135 AD31-AD25, 138-144, IO AD24, 1, AD23-AD16, 6-13, AD15-AD8, 26-33, AD7-AD0 37-44 FRAME# ...
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XR17V258 66MHZ PCI BUS OCTAL UART WITH POWER MANAGEMENT SUPPORT PIN DESCRIPTIONS AME IN YPE DTR0# 126 O DSR0# 130 CD0# 129 RI0# 128 TX1 117 O RX1 124 RTS1# 119 O CTS1# 123 DTR1# 118 ...
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PCI BUS OCTAL UART WITH POWER MANAGEMENT SUPPORT REV. 1.0.2 PIN DESCRIPTIONS AME IN YPE RI3# 95 TX4 88 O RX4 81 RTS4 CTS4# 82 DTR4 DSR4# 83 CD4# 84 RI4# ...
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XR17V258 66MHZ PCI BUS OCTAL UART WITH POWER MANAGEMENT SUPPORT PIN DESCRIPTIONS AME IN YPE RX7 47 RTS7 CTS7# 48 DTR7 DSR7# 49 CD7# 50 RI7# 51 ANCILLARY SIGNALS MPIO0 108 I/O ...
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PCI BUS OCTAL UART WITH POWER MANAGEMENT SUPPORT REV. 1.0.2 PIN DESCRIPTIONS AME IN YPE TMRCK 69 ENIR 70 VCC 64, 90,112, 4, 19, 34, 45, 137 GND 5,20,35,46,63, 89,136 N : Pin type: I=Input, ...
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XR17V258 66MHZ PCI BUS OCTAL UART WITH POWER MANAGEMENT SUPPORT FUNCTIONAL DESCRIPTION The XR17V258 (V258) consists of eight enhanced 16550 UARTs with a conventional PCI interface and a non- volatile memory interface for PCI plug-and-play auto-configuration. The PCI local bus ...
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PCI BUS OCTAL UART WITH POWER MANAGEMENT SUPPORT REV. 1.0.2 1.0 XR17V258 INTERNAL REGISTERS The XR17V258 UART has three different sets of registers as shown in Configuration Space Registers are for plug-and-play auto-configuration when connecting the device to the ...
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XR17V258 66MHZ PCI BUS OCTAL UART WITH POWER MANAGEMENT SUPPORT T 1: PCI L ABLE A DDRESS B T ITS YPE O FFSET 0x00 31:16 EWR Device ID (Exar device ID number) 15:0 EWR Vendor ID (Exar) specified by PCISIG ...
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PCI BUS OCTAL UART WITH POWER MANAGEMENT SUPPORT REV. 1.0 PCI L ABLE A DDRESS B T ITS YPE O FFSET 0x24 31:0 RO Unimplemented Base Address Register (returns zeros) 0x28 31:0 RO Reserved 0x2C 31:16 EWR ...
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XR17V258 66MHZ PCI BUS OCTAL UART WITH POWER MANAGEMENT SUPPORT T A DDRESS B T ITS YPE O FFSET 8 RWR 7:2 RO 1:0 RWR N : RWR=Read/Write from AD[31:0]. RO= Read Only. RWC=Read/Write-Clear. OTE 1.2.1 Power States and Power ...
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PCI BUS OCTAL UART WITH POWER MANAGEMENT SUPPORT REV. 1.0 TATE COLD The V258 enters the state when power is removed from the device. All context is lost in this state and the V258 does not support ...
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XR17V258 66MHZ PCI BUS OCTAL UART WITH POWER MANAGEMENT SUPPORT 1.4 EEPROM Interface The V258 provides an interface to an Electrically Erasable Programmable Read Only Memory (EEPROM). The EEPROM must be a 93C46-like device, with its memory configured as 16-bit ...
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PCI BUS OCTAL UART WITH POWER MANAGEMENT SUPPORT REV. 1.0 XR17V258 UART ABLE FFSET DDRESS EMORY PACE 0x000 - 0x00F UART channel 0 Regs 0x010 - 0x07F Reserved 0x080 - 0x093 DEVICE CONFIGURA- ...
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XR17V258 66MHZ PCI BUS OCTAL UART WITH POWER MANAGEMENT SUPPORT T 5: XR17V258 UART ABLE FFSET DDRESS EMORY PACE 0x800 - 0x80F UART channel 4 Regs 0x810 - 0x8FF Reserved 0x900 UART 4 – Read FIFO ...
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PCI BUS OCTAL UART WITH POWER MANAGEMENT SUPPORT REV. 1.0.2 1.6 Device Configuration Registers The Device Configuration Registers provide easy programming of general operating parameters to the V258 and for monitoring the status of various functions. These registers control ...
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XR17V258 66MHZ PCI BUS OCTAL UART WITH POWER MANAGEMENT SUPPORT ABLE EVICE A R DDRESS EGISTER - INTERRUPT (read-only) 0x080 083 0x084-087 TIMER (read/write) 0x088-08B ANCILLARY1 (read/write) 0x08C-08F ANCILLARY2 (read-only) 0x090-093 MPIO (read/write) 1.6.1 The Global ...
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PCI BUS OCTAL UART WITH POWER MANAGEMENT SUPPORT REV. 1.0 IGURE HE LOBAL NTERRUPT INT3 Register Channel-7 Channel-6 Channel-5 Bit Bit Bit Bit Bit Bit Bit Bit N+2 N+1 N N+2 N+1 N ...
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XR17V258 66MHZ PCI BUS OCTAL UART WITH POWER MANAGEMENT SUPPORT 1.6.2 General Purpose 16-bit Timer/Counter [TIMERMSB, TIMELSB, TIMER, TIMECNTL XX-XX-00-00) X The XR17V258 has a general purpose 16-bit timer/counter. The crystal/clock at the XTAL1 input or an external ...
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PCI BUS OCTAL UART WITH POWER MANAGEMENT SUPPORT REV. 1.0.2 TIMERCNTL [7:0] Register The bits [3:0] of this register are used to issue commands. The commands are self-clearing, so reading this register does not show the last written command. ...
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XR17V258 66MHZ PCI BUS OCTAL UART WITH POWER MANAGEMENT SUPPORT Timer Operation in Re-triggerable Mode: In the re-triggerable mode, when the Timer is started, the Timer output will stay HIGH until it reaches half of the terminal count N (= ...
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PCI BUS OCTAL UART WITH POWER MANAGEMENT SUPPORT REV. 1.0 IGURE NTERRUPT UTPUT ACTIVE Timer Started One-shot Mode Re-triggerable Mode 1.6.3 8XMODE [7:0] (default 0x00) Each bit selects 8X or 16X sampling rate for ...
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XR17V258 66MHZ PCI BUS OCTAL UART WITH POWER MANAGEMENT SUPPORT 1.6.6 SLEEP [31:24] (default 0x00) Ch-7 Bit-7 Bit-6 Bit-5 Bit-4 Bit-3 Bit-2 Bit-1 Bit-0 The 8-bit Sleep register enables each UART separately to enter Sleep mode. Sleep mode reduces power ...
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PCI BUS OCTAL UART WITH POWER MANAGEMENT SUPPORT REV. 1.0.2 1.6.8 REGB Register REGB[16](Read/Write) Logic 0 (default) write to each UART configuration registers individually. Logic 1 enables simultaneous write to all 8 UARTs configuration register. REGB[19:17] Reserved REGB[20] (Write-Only) ...
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XR17V258 66MHZ PCI BUS OCTAL UART WITH POWER MANAGEMENT SUPPORT IGURE ULTIPURPOSE INPUT MPIOINT [7:0] INT AND MPIOLVL [7:0] Read Input Level MPIOINV [7:0] (Input Inversion Enable =1) MPIOLVL [7:0] (Output Level) MPIO3T [7:0] (3-state Enable =1) ...
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PCI BUS OCTAL UART WITH POWER MANAGEMENT SUPPORT REV. 1.0.2 MPIO3T [7:0] (default 0x00) The MPIO outputs can be tri-stated by the MPIO3T register. A logic 0 (default) sets the output to active level per register MPIOBIT settling, a ...
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XR17V258 66MHZ PCI BUS OCTAL UART WITH POWER MANAGEMENT SUPPORT generators for standard or custom rates. Typically, the oscillator connections are shown in further reading on oscillator circuit please see application note DAN108 on EXAR’s web site. F IGURE 3.0 ...
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PCI BUS OCTAL UART WITH POWER MANAGEMENT SUPPORT REV. 1.0.2 (channel 2),......., 0xF00 (channel 7). This operation is at least 16 times faster than reading the data in 64 separate 8-bit memory reads of RHR register (0x000 for channel ...
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XR17V258 66MHZ PCI BUS OCTAL UART WITH POWER MANAGEMENT SUPPORT 3.1.3 Tx FIFO Data Loading at locations 0x100, 0x300, 0x500, 0x700, 0x900, 0xB00, 0xD00, 0xF00 The TX FIFO data (up to the maximum 64 bytes) can be loaded in a ...
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PCI BUS OCTAL UART WITH POWER MANAGEMENT SUPPORT REV. 1.0.2 T 11: T ABLE RANSMIT AND THR and RHR Address Locations For CH0 to CH7 (16C550 Compatible) CH0 0x000 Write THR CH0 0x000 Read RHR CH1 0x200 Write THR ...
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XR17V258 66MHZ PCI BUS OCTAL UART WITH POWER MANAGEMENT SUPPORT The closest divisor that is obtainable in the V258 can be calculated using the following formula: ROUND( (Required Divisor - TRUNC (Required Divisor) )*16)/16 + TRUNC (Required Divisor), where DLM ...
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PCI BUS OCTAL UART WITH POWER MANAGEMENT SUPPORT REV. 1.0.2 T 12: T ABLE YPICAL DATA RATES WITH 16x EQUIRED IVISOR FOR O D Clock O UTPUT ATA R (Decimal) ATE 400 2304 2400 384 4800 ...
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XR17V258 66MHZ PCI BUS OCTAL UART WITH POWER MANAGEMENT SUPPORT T 13: T ABLE YPICAL DATA RATES WITH 16x EQUIRED IVISOR FOR O D Clock O UTPUT ATA R (Decimal) ATE 400 3750 2400 625 4800 312.5 ...
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PCI BUS OCTAL UART WITH POWER MANAGEMENT SUPPORT REV. 1.0.2 4.2 Automatic Hardware (RTS/CTS or DTR/DSR) Flow Control Operation Automatic hardware or RTS/DTR and CTS/DSR flow control is used to prevent data overrun to the local receiver FIFO and ...
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XR17V258 66MHZ PCI BUS OCTAL UART WITH POWER MANAGEMENT SUPPORT F 12. A RTS/DTR CTS/DSR F IGURE UTO AND Local UART UARTA Receiver FIFO Trigger Reached Auto RTS Trigger Level Transmitter Auto CTS Monitor Assert RTS# to Begin Transmission 1 ...
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PCI BUS OCTAL UART WITH POWER MANAGEMENT SUPPORT REV. 1.0.2 The infrared decoder receives the input pulse from the infrared sensing diode on RX pin. Each time the decoder senses a light pulse, it returns a "0" to the ...
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XR17V258 66MHZ PCI BUS OCTAL UART WITH POWER MANAGEMENT SUPPORT F 14 IGURE NTERNAL OOP 4.5 UART CHANNEL CONFIGURATION REGISTERS AND ADDRESS DECODING The 8 sets of UART configuration registers are decoded using address lines A9 to A11 ...
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PCI BUS OCTAL UART WITH POWER MANAGEMENT SUPPORT REV. 1.0.2 T 14: UART CHANNEL CONFIGURATION REGISTERS. ABLE A DDRESS RHR - Receive Holding Register THR - Transmit Holding Register 0 0 ...
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XR17V258 66MHZ PCI BUS OCTAL UART WITH POWER MANAGEMENT SUPPORT T 15: UART CHANNEL CONFIGURATION REGISTERS DESCRIPTION. ABLE DDRESS EG EAD B [7] IT A3- AME RITE RHR R BIT ...
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PCI BUS OCTAL UART WITH POWER MANAGEMENT SUPPORT REV. 1.0.2 T 15: UART CHANNEL CONFIGURATION REGISTERS DESCRIPTION. ABLE DDRESS EG EAD B [7] IT A3- AME RITE EFR R/W ...
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XR17V258 66MHZ PCI BUS OCTAL UART WITH POWER MANAGEMENT SUPPORT F 15 IGURE RANSMITTER PERATION IN NON Data Byte 16X or 8X Clock (8XMODE Register) Transmit Shift Register (TSR) 4.6.3 Transmitter Operation in FIFO Mode The host may ...
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PCI BUS OCTAL UART WITH POWER MANAGEMENT SUPPORT REV. 1.0.2 4.7 Receiver The receiver section contains an 8-bit Receive Shift Register (RSR) and Receive Holding Register (RHR). The RSR uses the 16X or 8X clock for timing. It verifies ...
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XR17V258 66MHZ PCI BUS OCTAL UART WITH POWER MANAGEMENT SUPPORT 5.0 UART CONFIGURATION REGISTERS 5.1 Receive Holding Register (RHR) - Read only SEE”RECEIVER” ON PAGE 43. 5.2 Transmit Holding Register (THR) - Write only SEE”TRANSMITTER” ON PAGE 41. 5.3 Baud ...
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PCI BUS OCTAL UART WITH POWER MANAGEMENT SUPPORT REV. 1.0.2 IER[4]: Reserved IER[3]: Modem Status Interrupt Enable The Modem Status Register interrupt is issued whenever any of the delta bits of the MSR register (bits [3:0]) is set. • ...
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XR17V258 66MHZ PCI BUS OCTAL UART WITH POWER MANAGEMENT SUPPORT 5.5.1 Interrupt Generation: • LSR is by any of the LSR bits [4:1]. See IER bit [2] description on the previous page. • RXRDY trigger level. • ...
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PCI BUS OCTAL UART WITH POWER MANAGEMENT SUPPORT REV. 1.0.2 ISR[0]: Interrupt Status • Logic interrupt is pending and the ISR contents may be used as a pointer to the appropriate interrupt service routine. • Logic ...
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XR17V258 66MHZ PCI BUS OCTAL UART WITH POWER MANAGEMENT SUPPORT T 17: T ABLE RANSMIT AND T FCTR FCTR FCR RIGGER T BIT [7] BIT [6] BIT [7] ABLE Table Table ...
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PCI BUS OCTAL UART WITH POWER MANAGEMENT SUPPORT REV. 1.0.2 LCR[5]: TX and RX Parity Select If the parity bit is enabled, LCR bit [5] selects the forced parity format. • LCR bit [5] = logic 0, parity is ...
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XR17V258 66MHZ PCI BUS OCTAL UART WITH POWER MANAGEMENT SUPPORT 5.8 Modem Control Register (MCR) - Read/Write The MCR register is used for controlling the modem interface signals or general purpose inputs/outputs. MCR[7]: Clock Prescaler Select (requires EFR bit [4]=1) ...
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PCI BUS OCTAL UART WITH POWER MANAGEMENT SUPPORT REV. 1.0.2 MCR[1]: RTS# Output The RTS# pin may be used for automatic hardware flow control by enabled by EFR bit [6] and MCR bit [2]=0. If the modem interface is ...
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XR17V258 66MHZ PCI BUS OCTAL UART WITH POWER MANAGEMENT SUPPORT LSR[1]: Receiver Overrun Flag • Logic overrun error (default). • Logic 1 = Overrun error. A data overrun error condition occurred in the receive shift register. This ...
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PCI BUS OCTAL UART WITH POWER MANAGEMENT SUPPORT REV. 1.0.2 MSR[1]: Delta DSR# Input Flag • Logic change on DSR# input (default). • Logic 1 = The DSR# input has changed state since the last time ...
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XR17V258 66MHZ PCI BUS OCTAL UART WITH POWER MANAGEMENT SUPPORT MSR [3]: Transmitter Disable This bit can be used to disable the transmitter by halting the Transmit Shift Register (TSR). When this bit is set to a logic 1, the ...
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PCI BUS OCTAL UART WITH POWER MANAGEMENT SUPPORT REV. 1.0.2 FCTR[4]: Infrared RX Input Logic Select • Logic 0 = Select RX input as active HIGH encoded IrDA data, normal, (default). • Logic 1 = Select RX input as ...
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XR17V258 66MHZ PCI BUS OCTAL UART WITH POWER MANAGEMENT SUPPORT EFR[6]: Auto RTS or DTR Flow Control Enable RTS#/DTR# output may be used for hardware flow control by setting EFR bit [6] to logic 1. When Auto RTS/ DTR is ...
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PCI BUS OCTAL UART WITH POWER MANAGEMENT SUPPORT REV. 1.0.2 T ABLE EFR BIT [3] EFR BIT [2] EFR BIT [ ...
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XR17V258 66MHZ PCI BUS OCTAL UART WITH POWER MANAGEMENT SUPPORT 5.20 XCHAR REGISTER, READ ONLY This register gives the status of the last sent control character (Xon or Xoff) and the last received control character (Xon or Xoff). This register ...
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PCI BUS OCTAL UART WITH POWER MANAGEMENT SUPPORT REV. 1.0.2 REGISTERS RESET STATE DLL Bits [7:0] = 0x01 DLM Bits [7:0] = 0x00 DLD Bits [7:0] = 0x00 RHR Bits [7:0] = 0xXX THR Bits [7:0] = 0xXX IER ...
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XR17V258 66MHZ PCI BUS OCTAL UART WITH POWER MANAGEMENT SUPPORT ABSOLUTE MAXIMUM RATINGS Power Supply Range Voltage at Any Pin Operating Temperature Storage Temperature Package Dissipation Thermal Resistance (20x20x1.4mm 144-LQFP) ELECTRICAL CHARACTERISTICS DC ELECTRICAL CHARACTERISTICS FOR 3.3V SIGNALLING O O ...
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PCI BUS OCTAL UART WITH POWER MANAGEMENT SUPPORT REV. 1.0.2 AC ELECTRICAL CHARACTERISTICS FOR 3.3V SIGNALING O O TA=-40 + INDUSTRIAL GRADE S P YMBOL ARAMETER XTAL1 UART Crystal Oscillator ECLK External Clock I Switching Current ...
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XR17V258 66MHZ PCI BUS OCTAL UART WITH POWER MANAGEMENT SUPPORT F 19. PCI B C IGURE US ONFIGURATION CLK Host FRAME# Host AD[31:0] Host Target C/BE[3:0]# Host IRDY# Host TRDY# Target DEVSEL# Target CLK Host FRAME# Host AD[31:0] Host Target ...
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PCI BUS OCTAL UART WITH POWER MANAGEMENT SUPPORT REV. 1.0 IGURE EVICE ONFIGURATION AND CLK Host FRAME# Host AD[31:0] Address Host Target Bus C/BE[3:0]# Byte Enable# = BYTE CMD Host IRDY# Host ...
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XR17V258 66MHZ PCI BUS OCTAL UART WITH POWER MANAGEMENT SUPPORT F 21 IGURE EVICE ONFIGURATION REGISTERS TION CLK Host FRAME# Host Data AD[31:0] Address DWORD DWORD Host Target Bus C/BE[3:0]# Byte Enable# = DWORD CMD ...
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PCI BUS OCTAL UART WITH POWER MANAGEMENT SUPPORT REV. 1.0 IGURE EVICE ONFIGURATION CLK Host 1 FRAME# Host AD[31:0] AD Host Target C/BE[3:0]# Bus Byte Enable# = DWORD CMD Host IRDY# Host TRDY# Target DEVSEL# ...
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XR17V258 66MHZ PCI BUS OCTAL UART WITH POWER MANAGEMENT SUPPORT F 23. 3.3V PCI B C IGURE US LOCK 0.5VCC CLK 0.4VCC 0.3VCC T_val Output Delay T_on Tri-State Output Input (DC 66MH ) TO Z T_cyc T_low T_high Measurement Condition ...
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PCI BUS OCTAL UART WITH POWER MANAGEMENT SUPPORT REV. 1.0 IGURE RANSMIT ATA NTERRUPT AT START BIT TX Data TX Interrupt at Transmit Trigger Level F 25 IGURE ECEIVE ATA ...
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XR17V258 66MHZ PCI BUS OCTAL UART WITH POWER MANAGEMENT SUPPORT PACKAGE DIMENSIONS 108 109 144 Seating Plane Note: The control dimension is the millimeter column OTE SYMBOL ...
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... August 2010 1.0.2 EXAR Corporation reserves the right to make changes to the products contained in this publication in order to improve design, performance or reliability. EXAR Corporation assumes no responsibility for the use of any circuits described herein, conveys no license under any patent or other right, and makes no representation that the circuits are free of patent infringement. Charts and schedules contained here in are only for illustration purposes and may vary depending upon a user’ ...