XR17V258IV-F Exar Corporation, XR17V258IV-F Datasheet - Page 26

• Manufacturer Part Number: XR17V258IV-F
• Description: IC UART PCI BUS OCTAL 144LQFP
• Manufacturer: Exar Corporation
• Type: Octal UARTr

Specifications of XR17V258IV-F

• Number Of Channels: 8
• Package / Case: 144-LQFP
• Features: *
• Fifo's: 64 Byte
• Protocol: RS485
• Voltage - Supply: 3.3V, 5V
• With Auto Flow Control: Yes
• With Irda Encoder/decoder: Yes
• With False Start Bit Detection: Yes
• With Modem Control: Yes
• Mounting Type: Surface Mount
• Data Rate: 8 Mbps
• Supply Voltage (max): 3.6 V
• Supply Voltage (min): 3 V
• Supply Current: 4 mA
• Maximum Operating Temperature: + 85 C
• Minimum Operating Temperature: - 45 C
• Mounting Style: SMD/SMT
• Operating Supply Voltage: 3 V to 3.6 V
• No. Of Channels: 8
• Uart Features: Tx/Rx FIFO Counters
• Supply Voltage Range: 3V To 3.6V
• Operating Temperature Range: -40°C To +85°C
• Digital Ic Case Style: LQFP
• No. Of Pins: 144
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

XR17V258
66MHZ PCI BUS OCTAL UART WITH POWER MANAGEMENT SUPPORT
MPIOINT [7:0] (default 0x00)
The MPIOINT register enables the multipurpose input pin interrupt. If an MPIO pin is selected by MPIOSEL as
an input, then it can be selected to generate an interrupt. MPIOINT bit[0] enables input pin MPIO0 for interrupt,
and bit [7] enables input pin 7. No interrupt is enable if the pin is selected to be an output. The interrupt is edge
sensing and determined by MPIOINV and MPIOLVL registers. The MPIO interrupt clears after a read to
register MPIOLVL. The combination of MPIOLVL and MPIOINV determines the interrupt being active LOW or
active HIGH. Logic 0 (default) disables the pin’s interrupt and logic 1 enables it.
MPIOLVL [7:0] (default 0x00)
The MPIOLVL register controls the output pins and provides the input level status for the input pins. The status
of the input pin(s) is read on this register and output pins are controlled on this register. A logic 0 (default) sets
the output to LOW and a logic 1 sets the output pin to HIGH. The MPIO interrupt will clear upon reading this
register.
F
IGURE
MPIOINT [7:0]
MPIOLVL [7:0]
Read Input Level
MPIOINV [7:0]
(Input Inversion Enable =1)
MPIOLVL [7:0]
(Output Level)
MPIO3T [7:0]
(3-state Enable =1)
MPIOSEL [7:0]
(Select Input=1, Output=0 )
INT
9. M
ULTIPURPOSE INPUT
AND
Bit-7 Bit-6 Bit-5 Bit-4 Bit-3 Bit-2 Bit-1 Bit-0
MPIO7
Multipurpose Input/Output Interrupt Enable
MPIO6
MPIO5 MPIO4 MPIO3 MPIO2 MPIO1 MPIO0
Rising Edge
Detection
MPIOINT Register
OR
/
OUTPUT INTERNAL CIRCUIT
1
0
26
AND
Pin [7:0]
MPIO
MPIOCKT
REV. 1.0.2