XR17V258IV-F Exar Corporation, XR17V258IV-F Datasheet - Page 15

• Manufacturer Part Number: XR17V258IV-F
• Description: IC UART PCI BUS OCTAL 144LQFP
• Manufacturer: Exar Corporation
• Type: Octal UARTr

Specifications of XR17V258IV-F

• Number Of Channels: 8
• Package / Case: 144-LQFP
• Features: *
• Fifo's: 64 Byte
• Protocol: RS485
• Voltage - Supply: 3.3V, 5V
• With Auto Flow Control: Yes
• With Irda Encoder/decoder: Yes
• With False Start Bit Detection: Yes
• With Modem Control: Yes
• Mounting Type: Surface Mount
• Data Rate: 8 Mbps
• Supply Voltage (max): 3.6 V
• Supply Voltage (min): 3 V
• Supply Current: 4 mA
• Maximum Operating Temperature: + 85 C
• Minimum Operating Temperature: - 45 C
• Mounting Style: SMD/SMT
• Operating Supply Voltage: 3 V to 3.6 V
• No. Of Channels: 8
• Uart Features: Tx/Rx FIFO Counters
• Supply Voltage Range: 3V To 3.6V
• Operating Temperature Range: -40°C To +85°C
• Digital Ic Case Style: LQFP
• No. Of Pins: 144
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

REV. 1.0.2
0x000 - 0x00F
0x010 - 0x07F
0x080 - 0x093
0x094 - 0x0FF
0x100
0x100
0x140 - 0x17F
0x180 - 0x1FF
0x200 - 0x20F
0x210 - 0x2FF
0x300
0x300
0x340 - 0x37F
0x380 - 0x3FF
0x400 - 0x40F
0x410 - 0x4FF
0x500
0x500
0x540 - 0x57F
0x580 - 0x5FF
0x600 - 0x60F
0x610 - 0x6FF
0x700
0x700
0x740 - 0x77F
0x780 - 0x7FF
O
FFSET
A
DDRESS
UART channel 0 Regs
Reserved
DEVICE CONFIGURA-
TION REGISTERS
Reserved
UART 0 – Read FIFO
UART 0 – Write FIFO
Reserved
UART 0 – Read FIFO
with errors
UART channel 1 Regs
Reserved
UART 1 – Read FIFO
UART 1 – Write FIFO
Reserved
UART 1 – Read FIFO
with errors
UART channel 2 Regs
Reserved
UART 2 – Read FIFO
UART 2 – Write FIFO
Reserved
UART 2 – Read FIFO
with errors
UART channel 3 Regs
Reserved
UART 3 – Read FIFO
UART 3 – Write FIFO
Reserved
UART 3 – Read FIFO
with errors
T
M
ABLE
EMORY
5: XR17V258 UART
S
PACE
66MHZ PCI BUS OCTAL UART WITH POWER MANAGEMENT SUPPORT
(
(
(
(
R
Table 14
Table 14
Table 14
Table 14
Read-Only
Read-Only
Read-Only
Read-Only
Read-Only
Read-Only
Read-Only
Read-Only
Table 15
Write-Only
Table 15
Write-Only
Table 15
Write-Only
Table 15
Write-Only
(
EAD
Table 6
AND
/W
RITE
15
D
)
)
)
)
)
&
&
&
&
EVICE
C
D
ONFIGURATION
8/16//24/32
8/16/24/32
8/16/24/32
8/16/24/32
8/16/24/32
8/16/24/32
8/16/24/32
8/16/24/32
8/16/24/32
8/16/24/32
8/16/24/32
8/16/24/32
8/16/24/32
ATA
16/32
16/32
16/32
16/32
W
IDTH
First 8 regs are 16550 compatible
64 bytes of RX FIFO data
64 bytes of TX FIFO data
64 bytes of RX FIFO data + LSR
First 8 regs are 16550 compatible
64 bytes of RX FIFO data
64 bytes of TX FIFO data
64 bytes of RX FIFO data + LSR
First 8 regs are 16550 compatible
64 bytes of RX FIFO data
64 bytes of TX FIFO data
64 bytes of RX FIFO data + LSR
First 8 regs are 16550 compatible
64 bytes of RX FIFO data
64 bytes of TX FIFO data
64 bytes of RX FIFO data + LSR
R
EGISTERS
C
OMMENT
XR17V258