XR17V258IV-F Exar Corporation, XR17V258IV-F Datasheet - Page 42
![IC UART PCI BUS OCTAL 144LQFP](/photos/29/6/290685/xr17v358_sml.jpg)
XR17V258IV-F
Manufacturer Part Number
XR17V258IV-F
Description
IC UART PCI BUS OCTAL 144LQFP
Manufacturer
Exar Corporation
Type
Octal UARTr
Datasheet
1.XR17V258IVTR-F.pdf
(69 pages)
Specifications of XR17V258IV-F
Number Of Channels
8
Package / Case
144-LQFP
Features
*
Fifo's
64 Byte
Protocol
RS485
Voltage - Supply
3.3V, 5V
With Auto Flow Control
Yes
With Irda Encoder/decoder
Yes
With False Start Bit Detection
Yes
With Modem Control
Yes
Mounting Type
Surface Mount
Data Rate
8 Mbps
Supply Voltage (max)
3.6 V
Supply Voltage (min)
3 V
Supply Current
4 mA
Maximum Operating Temperature
+ 85 C
Minimum Operating Temperature
- 45 C
Mounting Style
SMD/SMT
Operating Supply Voltage
3 V to 3.6 V
No. Of Channels
8
Uart Features
Tx/Rx FIFO Counters
Supply Voltage Range
3V To 3.6V
Operating Temperature Range
-40°C To +85°C
Digital Ic Case Style
LQFP
No. Of Pins
144
Rohs Compliant
Yes
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Lead Free Status / RoHS Status
Lead free / RoHS Compliant, Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
XR17V258IV-F
Manufacturer:
EXAR
Quantity:
295
Company:
Part Number:
XR17V258IV-F
Manufacturer:
Exar Corporation
Quantity:
10 000
Part Number:
XR17V258IV-F
Manufacturer:
EXAR/艾科嘉
Quantity:
20 000
XR17V258
66MHZ PCI BUS OCTAL UART WITH POWER MANAGEMENT SUPPORT
The host may fill the transmit FIFO with up to 64 bytes of transmit data. The THR empty flag (LSR bit [5]) is set
whenever the FIFO is empty. The THR empty flag can generate a transmit empty interrupt (ISR bit [1]) when
the amount of data in the FIFO falls below its programmed trigger level (see TXTRG register). The transmit
empty interrupt is enabled by IER bit [1]. The TSR flag (LSR bit [6]) is set when TSR becomes completely
empty. Furthermore, with the RS485 half-duplex direction control enabled (FCTR bit [5]=1) the source of the
transmit empty interrupt changes to TSR empty instead of THR empty. This is to ensure the RTS# output is not
changed until the last stop bit of the last character is shifted out.
The auto RS485 half-duplex direction control changes the behavior of the transmitter when enabled by FCTR
bit [5]. It de-asserts RTS# or DTR# after a specified delay indicated in MSR[7:4] following the last stop bit of the
last character that has been transmitted. This helps in turning around the transceiver to receive the remote
station’s response. The delay optimizes the time needed for the last transmission to reach the farthest station
on a long cable network before switching off the line driver. This delay prevents undesirable line signal
disturbance that causes signal degradation. It also changes the transmitter empty interrupt to TSR empty
instead of THR empty.
F
4.6.3
4.6.4
IGURE
F
IGURE
15. T
16. T
(8XMODE
16X or 8X
Register)
Transmitter Operation in FIFO Mode
Auto RS485 Operation
Clock
(8XMODE Register)
(Xoff1/2 and Xon1/2 Reg.
Auto Software Flow Control
Auto CTS Flow Control (CTS# pin)
Flow Control Characters
RANSMITTER
16X or 8X Clock
RANSMITTER
Data
Byte
O
PERATION IN NON
O
Transmit Shift Register (TSR)
Data Byte
PERATION IN
Transmit
Transmit
Register
Holding
(THR)
FIFO
-FIFO M
Transmit Data Shift Register
AND
F
(64-Byte)
ODE
Transmit
LOW
42
FIFO
(TSR)
C
ONTROL
THR Interrupt (ISR bit-1)
Enabled by IER bit-1
M
ODE
THR Interrupt (ISR bit-1) falls
when becomes empty. FIFO
below Programmed Trigger
is Enabled by FCR bit-0=1
Level (TXTRG) and then
M
S
B
TXNOFIFO1
L
S
B
TXFIFO1
REV. 1.0.2