XR17V258IV-F Exar Corporation, XR17V258IV-F Datasheet - Page 53

• Manufacturer Part Number: XR17V258IV-F
• Description: IC UART PCI BUS OCTAL 144LQFP
• Manufacturer: Exar Corporation
• Type: Octal UARTr

Specifications of XR17V258IV-F

• Number Of Channels: 8
• Package / Case: 144-LQFP
• Features: *
• Fifo's: 64 Byte
• Protocol: RS485
• Voltage - Supply: 3.3V, 5V
• With Auto Flow Control: Yes
• With Irda Encoder/decoder: Yes
• With False Start Bit Detection: Yes
• With Modem Control: Yes
• Mounting Type: Surface Mount
• Data Rate: 8 Mbps
• Supply Voltage (max): 3.6 V
• Supply Voltage (min): 3 V
• Supply Current: 4 mA
• Maximum Operating Temperature: + 85 C
• Minimum Operating Temperature: - 45 C
• Mounting Style: SMD/SMT
• Operating Supply Voltage: 3 V to 3.6 V
• No. Of Channels: 8
• Uart Features: Tx/Rx FIFO Counters
• Supply Voltage Range: 3V To 3.6V
• Operating Temperature Range: -40°C To +85°C
• Digital Ic Case Style: LQFP
• No. Of Pins: 144
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

REV. 1.0.2
MSR[1]: Delta DSR# Input Flag
•
•
MSR[0]: Delta CTS# Input Flag
•
•
The upper four bits [7:4] of this register set the delay in number of bits time for the auto RS-485 turn around
from transmit to receive.
MSR [7:4]: Auto RS485 Turn-Around Delay (requires EFR bit [4]=1)
When Auto RS485 feature is enabled (FCTR bit [5]=1) and RTS# output is connected to the enable input of a
RS-485 transceiver. These 4 bits select from 0 to 15 bit-time delay after the end of the last stop-bit of the last
transmitted character. This delay controls when to change the state of RTS# output. This delay is very useful in
long-cable networks.
5.11
Logic 0 = No change on DSR# input (default).
Logic 1 = The DSR# input has changed state since the last time it was monitored. A modem status interrupt
will be generated if MSR interrupt is enabled (IER bit [3]).
Logic 0 = No change on CTS# input (default).
Logic 1 = The CTS# input has changed state since the last time it was monitored. A modem status interrupt
will be generated if MSR interrupt is enabled (IER bit [3]).
Modem Status Register (MSR) - Write Only
T
ABLE
19: A
UTO
Table 19
MSR[7]
RS485 H
0
0
0
0
0
9
0
0
1
1
1
1
1
1
1
1
shows the selection. The bits are enabled by EFR bit [4].
MSR[6]
66MHZ PCI BUS OCTAL UART WITH POWER MANAGEMENT SUPPORT
ALF
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
-
DUPLEX
MSR[5]
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
D
IRECTION
MSR[4]
53
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
C
ONTROL
D
ELAY IN
D
ELAY FROM
D
ATA
10
12
13
14
15
11
0
1
2
3
4
5
6
7
8
9
B
IT
T
(
S
RANSMIT
) T
IME
-
TO
-R
XR17V258
ECEIVE