XR17V258IV-F Exar Corporation, XR17V258IV-F Datasheet - Page 40

• Manufacturer Part Number: XR17V258IV-F
• Description: IC UART PCI BUS OCTAL 144LQFP
• Manufacturer: Exar Corporation
• Type: Octal UARTr

Specifications of XR17V258IV-F

• Number Of Channels: 8
• Package / Case: 144-LQFP
• Features: *
• Fifo's: 64 Byte
• Protocol: RS485
• Voltage - Supply: 3.3V, 5V
• With Auto Flow Control: Yes
• With Irda Encoder/decoder: Yes
• With False Start Bit Detection: Yes
• With Modem Control: Yes
• Mounting Type: Surface Mount
• Data Rate: 8 Mbps
• Supply Voltage (max): 3.6 V
• Supply Voltage (min): 3 V
• Supply Current: 4 mA
• Maximum Operating Temperature: + 85 C
• Minimum Operating Temperature: - 45 C
• Mounting Style: SMD/SMT
• Operating Supply Voltage: 3 V to 3.6 V
• No. Of Channels: 8
• Uart Features: Tx/Rx FIFO Counters
• Supply Voltage Range: 3V To 3.6V
• Operating Temperature Range: -40°C To +85°C
• Digital Ic Case Style: LQFP
• No. Of Pins: 144
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

A
XR17V258
66MHZ PCI BUS OCTAL UART WITH POWER MANAGEMENT SUPPORT
0 0 0 0
0 0 0 0
0 0 0 0
0 0 0 1
0 0 1 0
0 0 0 1
0 0 1 0
0 0 1 0
0 0 1 1
0 1 0 0
0 1 0 1
0 1 1 0
0 1 1 1
1 0 0 0
A3-A0
T
DDRESS
ABLE
15: UART CHANNEL CONFIGURATION REGISTERS DESCRIPTION.
FCTR
N
MCR
MSR
MSR
RHR
THR
DLM
FCR
SPR
DLD
LCR
LSR
R
DLL
IER
ISR
AME
EG
W
R
R/W
R/W
R/W
R/W
R/W
R/W
R/W RX FIFO
R/W
R/W
EAD
RITE
W
W
W
R
R
R
/
RX FIFO
Enable
Enable
Trigger
Divisor
Enable
E
RS485
B
BIT [7]
BIT [7]
BIT [7]
BIT [7]
FIFOs
DSR#
DLY-3
Bit [7]
Pres-
Table
CTS/
BRG
caler
Bit [1]
TRG
RROR
IT
Int.
CD
0/
0/
0
[7]
RX FIFO
Enable
Enable
Trigger
Enable
B
BIT [6]
BIT [6]
BIT [6]
BIT [6]
Set TX
RS485
Empty
FIFOs
DLY-2
DTR#
Break
Bit [6]
Bit [0]
Table
RTS/
TRG
TSR
IT
Int.
IR
RI
0/
0/
0
[6]
Char. Int.
TX FIFO
Set Par-
Xoff/Sp.
XonAny
Trigger
Enable
RS485
RS485
Enable
B
Empty
Delta-
DLY-1
Bit [5]
Bit [5]
Bit [5]
Bit [5]
Bit [5]
Xon/
Flow
THR
DSR
Auto
Cntl
IT
ity
0/
0/
0/
0/
0
[5]
Even Par-
Loopback
RX Break
Xoff/spe-
RX Input
TX FIFO
Invert IR
cial char
40
Internal
Trigger
Enable
RS485
B
DLY-0
Bit [4]
Bit [4]
Bit [4]
Bit [4]
Bit [4]
CTS
IT
ity
0/
0/
0
0
[4]
Immedi-
Framing
TX char
Modem
Disable
Source
Enable
Enable
(OP2)
B
Status
Bit [3]
Bit [3]
Bit [3]
Bit [3]
Bit [3]
Bit [3]
Mode
Parity
Bit [3]
Bit [3]
Delta
DMA
Error
RTS/
DTR
CD#
Hyst
INT
IT
Int.
ate
RX
TX
[3]
1
Stop Bits
TX FIFO
Flow Sel
RX Line
RX Par-
ity Error
Disable
Enable
Source
(OP1)
B
Status
Bit [2]
Bit [2]
Bit [2]
Bit [2]
Bit [2]
Bit [2]
Reset
Bit [2]
Bit [2]
RTS/
Delta
RTS/
DTR
DTR
Hyst
INT
RI#
IT
Int.
RX
[2]
1
S
HADED BITS ARE ENABLED BY
RX FIFO
Pin Con-
Overrun
Source
Enable
Length
Empty
B
Reset
DSR#
Bit [1]
Bit [1]
Bit [1]
Bit [1]
Bit [1]
Bit [1]
Bit [1]
RTS#
Bit [1]
Bit [1]
Word
Delta
RTS/
DTR
Hyst
INT
Int.
trol
RX
IT
TX
[1]
Pin Con-
RX Data
RX Data
Enable
Source
Enable
Length
B
FIFOs
Ready
Bit [0]
Bit [0]
Bit [0]
Bit [0]
Bit [0]
Bit [0]
Bit [0]
DTR#
CTS#
Bit [0]
Bit [0]
Word
Delta
RTS/
DTR
Hyst
INT
IT
Int.
trol
[0]
REV. 1.0.2
User Data
LCR[7]=0
LCR[7]=0
LCR[7]=1
LCR[7]=1
LCR[7]=1
LCR[7]=0
LCR[7]=0
LCR[7]=0
EFR B
C
OMMENT
IT
-4.