ATTINY461-20PU Atmel, ATTINY461-20PU Datasheet - Page 27

• Manufacturer Part Number: ATTINY461-20PU
• Description: Microcontrollers (MCU) 4kB Flash 0.256kB EEPROM 16 I/O Pins
• Manufacturer: Atmel

Specifications of ATTINY461-20PU

• Processor Series: ATTINY4x
• Core: AVR8
• Data Bus Width: 8 bit
• Data Ram Size: 256 B
• Interface Type: 2-Wire/SPI/USI
• Maximum Clock Frequency: 20 MHz
• Number Of Programmable I/os: 16
• Number Of Timers: 2
• Operating Supply Voltage: 4.5 V to 5.5 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: Through Hole
• 3rd Party Development Tools: EWAVR, EWAVR-BL
• Development Tools By Supplier: ATAVRDRAGON, ATSTK500, ATSTK600, ATAVRISP2, ATAVRONEKIT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 11-ch x 10-bit
• Program Memory Type: Flash
• Program Memory Size: 4 KB
• Package / Case: PDIP-20
• Package: 20PDIP
• Device Core: AVR
• Family Name: ATtiny
• Maximum Speed: 20 MHz
• Ram Size: 256 Byte
• Operating Temperature: -40 to 85 °C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

2588E–AVR–08/10
The fast peripheral clock, clk
prescaled version of the PLL output, clk
a detailed illustration on the PLL clock system.
Figure 6-3.
The internal PLL is enabled when CKSEL fuse bits are programmed to ‘0001’and the PLLE bit of
PLLCSR is set. The internal oscillator and the PLL are switched off in power down and stand-by
sleep modes.
When the LSM bit of PLLCSR is set, the PLL switches from using the output of the internal 8
MHz oscillator to using the output divided by two. The frequency of the fast peripheral clock is
effectively divided by two, resulting in a clock frequency of 32 MHz. The LSM bit can not be set if
PLL
Since the PLL is locked to the output of the internal 8 MHz oscillator, adjusting the oscillator fre-
quency via the OSCCAL register also changes the frequency of the fast peripheral clock. It is
possible to adjust the frequency of the internal oscillator to well above 8 MHz but the fast periph-
eral clock will saturate and remain oscillating at about 85 MHz. In this case the PLL is no longer
locked to the internal oscillator clock signal. Therefore, in order to keep the PLL in the correct
operating range, it is recommended to program the OSCCAL registers such that the oscillator
frequency does not exceed 8 MHz.
The PLOCK bit in PLLCSR is set when PLL is locked.
Programming CKSEL fuse bits to ‘0001’, the PLL output divided by four will be used as a system
clock, as shown in
Table 6-4.
XTAL1
XTAL2
CLK
is used as a system clock.
OSCCAL
OSCILLATORS
OSCILLATOR
8 MHz
CKSEL3:0
PCK Clocking System
PLLCK Operating Modes
0001
Table
LSM
6-4.
1/2
PCK
4 MHz
8 MHz
, can be selected as the clock source for Timer/Counter1 and a
PLL
, can be selected as system clock. See
PLLE
PLL
8x
64 / 32 MHz
Nominal Frequency
DETECTOR
1/4
LOCK
16 MHz
16 MHz
8 MHz
CKSEL3:0
PRESCALER
CLKPS3:0
Figure 6-3
PLOCK
clk
clk
PCK
PLL
for
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