ATTINY461-20PU Atmel, ATTINY461-20PU Datasheet - Page 71

• Manufacturer Part Number: ATTINY461-20PU
• Description: Microcontrollers (MCU) 4kB Flash 0.256kB EEPROM 16 I/O Pins
• Manufacturer: Atmel

Specifications of ATTINY461-20PU

• Processor Series: ATTINY4x
• Core: AVR8
• Data Bus Width: 8 bit
• Data Ram Size: 256 B
• Interface Type: 2-Wire/SPI/USI
• Maximum Clock Frequency: 20 MHz
• Number Of Programmable I/os: 16
• Number Of Timers: 2
• Operating Supply Voltage: 4.5 V to 5.5 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: Through Hole
• 3rd Party Development Tools: EWAVR, EWAVR-BL
• Development Tools By Supplier: ATAVRDRAGON, ATSTK500, ATSTK600, ATAVRISP2, ATAVRONEKIT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 11-ch x 10-bit
• Program Memory Type: Flash
• Program Memory Size: 4 KB
• Package / Case: PDIP-20
• Package: 20PDIP
• Device Core: AVR
• Family Name: ATtiny
• Maximum Speed: 20 MHz
• Ram Size: 256 Byte
• Operating Temperature: -40 to 85 °C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

11. Timer/Counter0
11.1
11.2
11.2.1
2588E–AVR–08/10
Features
Overview
Registers
•
•
•
•
•
Timer/Counter0 is a general purpose 8/16-bit Timer/Counter module, with two/one Output Com-
pare units and Input Capture feature.
The general operation of Timer/Counter0 is described in 8/16-bit mode. A simplified block dia-
gram of the 8/16-bit Timer/Counter is shown in
including I/O bits and I/O pins, are shown in bold. For actual placement of I/O pins, refer to
out ATtiny261/461/861 and ATtiny261V/461V/861V” on page
bit locations are listed in the
Figure 11-1. 8-/16-bit Timer/Counter Block Diagram
The Timer/Counter0 Low Byte Register (TCNT0L) and Output Compare Registers (OCR0A and
OCR0B) are 8-bit registers. Interrupt request (abbreviated Int.Req. in
Clear Timer on Compare Match (Auto Reload)
One Input Capture unit
Four Independent Interrupt Sources (TOV0, OCF0A, OCF0B, ICF0)
8-bit Mode with Two Independent Output Compare Units
16-bit Mode with One Independent Output Compare Unit
TCCRnA
TCNTnH
OCRnB
=
Timer/Counter
“Register Description” on page
Direction
Count
Clear
TCNTnL
TCCRnB
OCRnA
=
Control Logic
TOP
Figure
Detector
Edge
clk
=
Tn
11-1. CPU accessible I/O Registers,
84.
2. Device-specific I/O Register and
Canceler
Fixed TOP value
( From Prescaler )
Noise
Figure
Clock Select
Detector
Edge
TOVn (Int. Req.)
11-1) signals are all
Comparator Ouput )
OCnA (Int. Req.)
OCnB (Int. Req.)
ICFn (Int. Req.)
( From Analog
ICPn
Tn
“Pin-
71