IPR-SDRAM/HPDDR2 Altera, IPR-SDRAM/HPDDR2 Datasheet - Page 12

• Manufacturer Part Number: IPR-SDRAM/HPDDR2
• Description: IP CORE Renewal Of IP-SDRAM/HDDR2
• Manufacturer: Altera

Specifications of IPR-SDRAM/HPDDR2

• Software Application: IP CORE, Memory Controllers, SDRAM
• Supported Families: Stratix FPGAs, Quartus II
• Core Architecture: FPGA
• Core Sub-architecture: Arria, Cyclone, Stratix
• Rohs Compliant: NA
• Lead Free Status / RoHS Status: na

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OpenCore Plus Time-Out Behavior
DDR and DDR2 SDRAM High-Performance Controller User Guide
f
1
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You need to purchase a license for the megafunction only when you are completely
satisfied with its functionality and performance, and want to take your design to
production.
For more information on OpenCore Plus hardware evaluation using the DDR and
DDR2 SDRAM high-performance controller, refer to
of
OpenCore Plus hardware evaluation can support the following two modes of
operation:
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■
All megafunctions in a device time out simultaneously when the most restrictive
evaluation time is reached. If there is more than one megafunction in a design, a
specific megafunction’s time-out behavior may be masked by the time-out behavior
of the other megafunctions.
For MegaCore functions, the untethered time-out is 1 hour; the tethered time-out
value is indefinite.
Your design stops working after the hardware evaluation time expires and the
local_ready output goes low.
Megafunctions.
Program a device and verify your design in hardware
Untethered—the design runs for a limited time
Tethered—requires a connection between your board and the host computer. If
tethered mode is supported by all megafunctions in a design, the device can
operate for a longer time or indefinitely
Chapter 1: About These MegaCore Functions
AN320: OpenCore Plus Evaluation
© March 2009 Altera Corporation
Installation and Licensing