IPR-SDRAM/HPDDR2 Altera, IPR-SDRAM/HPDDR2 Datasheet - Page 8

• Manufacturer Part Number: IPR-SDRAM/HPDDR2
• Description: IP CORE Renewal Of IP-SDRAM/HDDR2
• Manufacturer: Altera

Specifications of IPR-SDRAM/HPDDR2

• Software Application: IP CORE, Memory Controllers, SDRAM
• Supported Families: Stratix FPGAs, Quartus II
• Core Architecture: FPGA
• Core Sub-architecture: Arria, Cyclone, Stratix
• Rohs Compliant: NA
• Lead Free Status / RoHS Status: na

1–4
Performance and Resource Utilization
Table 1–3. Maximum Performance for Half Rate and Full Rate Controllers
Table 1–4. Resource Utilization in Arria GX Devices
DDR and DDR2 SDRAM High-Performance Controller User Guide
Arria GX
Cyclone III
HardCopy II
Stratix II
Stratix II GX
Stratix III
Stratix IV
Controller Rate
Half
Full
Device
f
Width (Bits)
Local Data
Table 1–3
high-performance controllers using the Quartus II software, version 9.0 with
Arria GX, Cyclone III, HardCopy II, Stratix II, Stratix II GX, Stratix III, and Stratix IV
devices.
For more information on device performance, refer to the relevant device handbook.
Table 1–4
controller in AFI mode (including ALTMEMPHY) for Arria GX devices.
256
288
256
288
32
64
32
64
Half Rate
200
200
200
200
200
200
167
shows maximum performance results for the DDR and DDR2 SDRAM
shows typical sizes for the DDR or DDR2 SDRAM high-performance
Memory Width
DDR SDRAM
(Bits)
16
64
72
16
64
72
8
8
Full Rate
167
167
200
200
200
200
200
Combinational
System f
ALUTs
1,851
1,904
2,208
2,289
1,662
1,666
1,758
1738
MAX
(MHz)
Half Rate
Dedicated Logic
233
200
267
333
333
400
400
Chapter 1: About These MegaCore Functions
Registers
1,562
1,738
2,783
2,958
1,332
1,421
1,939
2,026
DDR2 SDRAM
Performance and Resource Utilization
© March 2009 Altera Corporation
M512
4
4
5
4
6
3
3
4
Full Rate
Memory
167
167
267
267
267
267
267
M4K
15
17
2
4
0
3
9
9