IPR-SDRAM/HPDDR2 Altera, IPR-SDRAM/HPDDR2 Datasheet - Page 35

• Manufacturer Part Number: IPR-SDRAM/HPDDR2
• Description: IP CORE Renewal Of IP-SDRAM/HDDR2
• Manufacturer: Altera

Specifications of IPR-SDRAM/HPDDR2

• Software Application: IP CORE, Memory Controllers, SDRAM
• Supported Families: Stratix FPGAs, Quartus II
• Core Architecture: FPGA
• Core Sub-architecture: Arria, Cyclone, Stratix
• Rohs Compliant: NA
• Lead Free Status / RoHS Status: na

Chapter 4: Functional Description
Block Description
Error Correction Coding (ECC)
© March 2009 Altera Corporation
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1
The exact latency depends on your precise configuration. You should obtain precise
latency from simulation, but this figure may vary in hardware because of the
automatic calibration process.
Refer to the Latency section in chapter 1 of the
Megafunction User Guide (ALTMEMPHY)
The optional ECC comprises an encoder and a decoder-corrector, which can detect
and correct single-bit errors and detect double-bit errors. The ECC uses an 8-bit ECC
for each 64-bit message. The ECC has the following features:
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Hamming code ECC that encodes every 64-bits of data into 72-bits of codeword
with 8-bits of Hamming code parity bits
Latency:
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Detects and corrects all single-bit errors. Also the ECC sends an interrupt when
the user-defined threshold for a single-bit error is reached.
Detects all double-bit errors. Also, the ECC counts the number of double-bit errors
and sends an interrupt when the user-define threshold for double-bit error is
reached.
Accepts partial writes
Creates forced errors to check the functioning of the ECC
Powers up in a sensible state
Maximum of 1 or 2 clock delay during writes
Minimum 1 or 3 clock delay during reads
DDR and DDR2 SDRAM High-Performance Controller User Guide
for more detailed information.
External Memory PHY Interface
4–7