IPR-SDRAM/HPDDR2 Altera, IPR-SDRAM/HPDDR2 Datasheet - Page 6
![no-image](/images/manufacturer_photos/0/0/40/altera_sml.jpg)
IPR-SDRAM/HPDDR2
Manufacturer Part Number
IPR-SDRAM/HPDDR2
Description
IP CORE Renewal Of IP-SDRAM/HDDR2
Manufacturer
Altera
Datasheet
1.IP-SDRAMHPDDR.pdf
(88 pages)
Specifications of IPR-SDRAM/HPDDR2
Software Application
IP CORE, Memory Controllers, SDRAM
Supported Families
Stratix FPGAs, Quartus II
Core Architecture
FPGA
Core Sub-architecture
Arria, Cyclone, Stratix
Rohs Compliant
NA
Lead Free Status / RoHS Status
na
- Current page: 6 of 88
- Download datasheet (4Mb)
1–2
Features
General Description
DDR and DDR2 SDRAM High-Performance Controller User Guide
f
Table 1–2. Device Family Support (Part 2 of 2)
■
■
■
■
■
■
■
■
■
■
■
■
■
■
■
■
The Altera DDR and DDR2 SDRAM High-Performance Controller MegaCore
functions provide simplified interfaces to industry-standard DDR SDRAM and DDR2
SDRAM. The MegaCore functions work in conjunction with the Altera ALTMEMPHY
megafunction.
For more information on the ALTMEMPHY megafunction, refer to the
Memory PHY Interface Megafunction User Guide
Stratix
Stratix II GX
Stratix III
Stratix IV
Other device families
Integrated error correction coding (ECC) function
Power-up calibrated on-chip termination (OCT) support for Cyclone III, Stratix III,
and Stratix IV devices
Full-rate and half-rate support
SOPC Builder ready
Support for ALTMEMPHY megafunction
Support for industry-standard DDR and DDR2 SDRAM devices; and registered
and unbuffered DIMMs
Optional support for self-refresh and power-down commands
Optional support for auto-precharge read and auto-precharge write commands
Optional user-controller refresh
Optional Avalon
Optional Altera PHY interface (AFI) Controller-PHY Interface
Optional multiple controller clock sharing in SOPC Builder Flow
Easy-to-use MegaWizard
Support for OpenCore Plus evaluation
Support for the Quartus II IP Advisor
IP functional simulation models for use in Altera-supported VHDL and Verilog
HDL simulators
®
II
Device Family
®
Memory-Mapped (Avalon-MM) local interface
TM
interface
Full
Full
Full
Preliminary
No support
(ALTMEMPHY).
Chapter 1: About These MegaCore Functions
© March 2009 Altera Corporation
Support
External
Features
Related parts for IPR-SDRAM/HPDDR2
Image
Part Number
Description
Manufacturer
Datasheet
Request
R
![IPR-SDRAM/DDR](/images/manufacturer_photos/0/0/40/altera_tmb.jpg)
Part Number:
Description:
IP CORE Renewal Of IP-SDRAM/DDR
Manufacturer:
Altera
Datasheet:
![IPR-SDRAM/DDR2](/images/manufacturer_photos/0/0/40/altera_tmb.jpg)
Part Number:
Description:
IP CORE Renewal Of IP-SDRAM/DDR2
Manufacturer:
Altera
Datasheet:
![IPR-SDRAM/HPDDR](/images/manufacturer_photos/0/0/40/altera_tmb.jpg)
Part Number:
Description:
IP CORE Renewal Of IP-SDRAM/HPDDR
Manufacturer:
Altera
Datasheet:
![IPR-RLDRAMII](/images/manufacturer_photos/0/0/40/altera_tmb.jpg)
Part Number:
Description:
IP CORE Renewal Of IP-RLDRAMII
Manufacturer:
Altera
Datasheet:
![IPR-HPMCII](/photos/24/19/241941/4696148_tmb.jpg)
Part Number:
Description:
IP CORE Renewal Of IP-HPMCII
Manufacturer:
Altera
Datasheet:
![IPR-RLDII/UNI](/photos/24/19/241946/4696147_tmb.jpg)
Part Number:
Description:
IP CORE Renewal Of IP-RLDII/UNI
Manufacturer:
Altera
Datasheet:
![IPR-SRAM/QDRII](/images/manufacturer_photos/0/0/40/altera_tmb.jpg)
Part Number:
Description:
IP CORE Renewal Of IP-SRAM/QDRII
Manufacturer:
Altera
Datasheet:
![DK-CYCII-2C20N](/photos/9/20/92074/mfgdk-cycii-2c20nboard_tmb.jpg)
Part Number:
Description:
CYCLONE II STARTER KIT EP2C20N
Manufacturer:
Altera
Datasheet:
![EP610PC-35](/images/manufacturer_photos/0/0/41/altera_corporation_tmb.jpg)
Part Number:
Description:
CPLD, EP610 Family, ECMOS Process, 300 Gates, 16 Macro Cells, 16 Reg., 16 User I/Os, 5V Supply, 35 Speed Grade, 24DIP
Manufacturer:
Altera Corporation
Datasheet:
![EP610PC-15](/images/manufacturer_photos/0/0/41/altera_corporation_tmb.jpg)
Part Number:
Description:
CPLD, EP610 Family, ECMOS Process, 300 Gates, 16 Macro Cells, 16 Reg., 16 User I/Os, 5V Supply, 15 Speed Grade, 24DIP
Manufacturer:
Altera Corporation
Datasheet:
![EP610IPC-25](/images/manufacturer_photos/0/0/41/altera_corporation_tmb.jpg)
Part Number:
Description:
Manufacturer:
Altera Corporation
Datasheet:
![EP610PC-30](/images/manufacturer_photos/0/0/41/altera_corporation_tmb.jpg)
Part Number:
Description:
CPLD, EP610 Family, ECMOS Process, 300 Gates, 16 Macro Cells, 16 Reg., 16 User I/Os, 5V Supply, 30 Speed Grade, 24DIP
Manufacturer:
Altera Corporation
Datasheet:
![EP220PC-10](/images/manufacturer_photos/0/0/41/altera_corporation_tmb.jpg)
Part Number:
Description:
High-performance, low-power erasable programmable logic devices with 8 macrocells, 10ns
Manufacturer:
Altera Corporation
Datasheet: