IPR-SDRAM/HPDDR2 Altera, IPR-SDRAM/HPDDR2 Datasheet - Page 33

• Manufacturer Part Number: IPR-SDRAM/HPDDR2
• Description: IP CORE Renewal Of IP-SDRAM/HDDR2
• Manufacturer: Altera

Specifications of IPR-SDRAM/HPDDR2

• Software Application: IP CORE, Memory Controllers, SDRAM
• Supported Families: Stratix FPGAs, Quartus II
• Core Architecture: FPGA
• Core Sub-architecture: Arria, Cyclone, Stratix
• Rohs Compliant: NA
• Lead Free Status / RoHS Status: na

Chapter 4: Functional Description
Block Description
Control Logic
Latency
© March 2009 Altera Corporation
f
Bus commands control SDRAM devices using combinations of the mem_ras_n,
mem_cas_n, and mem_we_n signals. For example, on a clock cycle where all three
signals are high, the associated command is a no operation (NOP). A NOP command
is also indicated when the chip select signal is not asserted.
standard SDRAM bus commands.
Table 4–1. Bus Commands
The DDR and DDR2 SDRAM high-performance controllers must open SDRAM banks
before they access addresses in that bank. The row and bank to be opened are
registered at the same time as the active (ACT) command. The DDR and DDR2
SDRAM high-performance controllers close the bank and open it again if they need to
access a different row. The precharge (PCH) command closes only a bank.
The primary commands used to access SDRAM are read (RD) and write (WR). When
the WR command is issued, the initial column address and data word is registered.
When a RD command is issued, the initial address is registered. The initial data
appears on the data bus 2 to 3 clock cycles later (3 to 5 for DDR2 SDRAM). This delay
is the column address strobe (CAS) latency and is due to the time required to read the
internal DRAM core and register the data on the bus. The CAS latency depends on the
speed of the SDRAM and the frequency of the memory clock. In general, the faster the
clock, the more cycles of CAS latency are required. After the initial RD or WR
command, sequential reads and writes continue until the burst length is reached or a
burst terminate (BT) command is issued. DDR and DDR2 SDRAM devices support
burst lengths of 2, 4, or 8 data cycles. The auto-refresh command (ARF) is issued
periodically to ensure data retention. This function is performed by the DDR or DDR2
SDRAM high-performance controller.
The load mode register command (LMR) configures the SDRAM mode register. This
register stores the CAS latency, burst length, and burst type.
For more information, refer to the specification of the SDRAM that you are using.
There are two types of latency that you must consider for memory controller
designs—read and write latencies. We define the read and write latencies as follows.
■
No operation
Active
Read
Write
Burst terminate
Precharge
Auto refresh
Load mode register
Read latency is the time it takes for the read data to appear at the local interface
after you assert the read request signal to the controller.
Command
Acronym
NOP
LMR
PCH
ACT
ARF
WR
RD
BT
DDR and DDR2 SDRAM High-Performance Controller User Guide
ras_n
High
High
High
High
Low
Low
Low
Low
Table 4–1
cas_n
High
High
High
High
Low
Low
Low
Low
shows the
we_n
High
High
High
High
Low
Low
Low
Low
4–5