IPR-SDRAM/HPDDR2 Altera, IPR-SDRAM/HPDDR2 Datasheet - Page 71

• Manufacturer Part Number: IPR-SDRAM/HPDDR2
• Description: IP CORE Renewal Of IP-SDRAM/HDDR2
• Manufacturer: Altera

Specifications of IPR-SDRAM/HPDDR2

• Software Application: IP CORE, Memory Controllers, SDRAM
• Supported Families: Stratix FPGAs, Quartus II
• Core Architecture: FPGA
• Core Sub-architecture: Arria, Cyclone, Stratix
• Rohs Compliant: NA
• Lead Free Status / RoHS Status: na

Chapter 4: Functional Description
Interfaces and Signals
Table 4–8. DDR and DDR2 SDRAM Interface Signals (Part 2 of 2)
© March 2009 Altera Corporation
mem_we_n
Note to
(1) The mem_clk signals are output only signals from the FPGA. However, in the Quartus II software they must be defined as bidirectional (INOUT)
I/Os to support the mimic path structure that the ALTMEMPHY megafunction uses.
Signal Name
Table
4–8:
Table 4–9
Table 4–9. ECC Controller Signals
ecc_addr[]
ecc_be[]
ecc_interrupt
ecc_rdata[]
ecc_read_req
ecc_wdata[]
ecc_write_req
Direction
Output
Signal Name
shows the ECC controller signals.
Memory write enable signal.
Direction
Output
Output
Input
Input
Input
Input
Input
DDR and DDR2 SDRAM High-Performance Controller User Guide
Description
Address for ECC controller.
ECC controller byte enable.
Interrupt from ECC controller.
Return data from ECC controller.
Read request for ECC controller.
ECC controller write data.
Write request for ECC controller.
Description
4–43