IPR-SDRAM/HPDDR2 Altera, IPR-SDRAM/HPDDR2 Datasheet - Page 27

• Manufacturer Part Number: IPR-SDRAM/HPDDR2
• Description: IP CORE Renewal Of IP-SDRAM/HDDR2
• Manufacturer: Altera

Specifications of IPR-SDRAM/HPDDR2

• Software Application: IP CORE, Memory Controllers, SDRAM
• Supported Families: Stratix FPGAs, Quartus II
• Core Architecture: FPGA
• Core Sub-architecture: Arria, Cyclone, Stratix
• Rohs Compliant: NA
• Lead Free Status / RoHS Status: na

Memory Settings
PHY Settings
Controller Settings
Table 3–1. Controller Settings
© March 2009 Altera Corporation
Enable error detection and
correction logic
Enable user auto-refresh
controls
Enable auto-precharge
control
Enable power down controls
Enable self-refresh controls
Local Interface Protocol
Controller/Phy Interface
Protocol
Multiple Controller Clock
Sharing
Parameter
f
f
The Memory Settings page provides the same options as the ALTMEMPHY
megafunction Memory Settings page.
For more information on the memory settings, refer to the
Interface Megafunction User Guide
Board skew is the skew across all the memory interface signals, which includes clock,
address, command, data, mask, and strobe signals.
For more information on the PHY settings, refer to the
Megafunction User Guide
Table 3–1
Memory-Mapped
Native or Avalon
AFI or non-AFI
shows the options provided in the Controller Settings page.
On or off
On or off
On or off
On or off
On or off
On or off
Range
Turn on to add the optional error correction coding (ECC) to the design,
refer to
Turn on for user control of the refreshes, refer to
on page
Turn on if you need fast random access, refer to
Commands” on page 4–36
Turn on to enable the controller to allow you to place the external
memory device in a power-down mode, refer to
Power-Down Commands” on page 4–35
Turn on to enable the controller to allow you to place the external
memory device in a self-refresh mode, refer to
Down Commands” on page 4–35
Specifies the local side interface between the user logic and the memory
controller. The Avalon Memory-Mapped (MM) interface allows you to
easily connect to other Avalon-MM peripherals.
Specifies the controller/PHY interface. Refer to the
PHY Interface Megafunction User Guide (ALTMEMPHY)
information.
This option is only in SOPC Builder Flow. Turn on if you want to improve
your system efficiency when your system has multiple controllers. Refer
to the
(ALTMEMPHY)
(ALTMEMPHY).
External Memory PHY Interface Megafunction User Guide
“Error Correction Coding (ECC)” on page
4–34.
(ALTMEMPHY).
for more information.
DDR and DDR2 SDRAM High-Performance Controller User Guide
Description
3. Parameter Settings
External Memory PHY Interface
External Memory PHY
“Self-Refresh and Power-
“Self-Refresh and
“Auto-Precharge
“User Refresh Control”
4–7.
External Memory
for more