IPR-SDRAM/HPDDR2 Altera, IPR-SDRAM/HPDDR2 Datasheet - Page 39

• Manufacturer Part Number: IPR-SDRAM/HPDDR2
• Description: IP CORE Renewal Of IP-SDRAM/HDDR2
• Manufacturer: Altera

Specifications of IPR-SDRAM/HPDDR2

• Software Application: IP CORE, Memory Controllers, SDRAM
• Supported Families: Stratix FPGAs, Quartus II
• Core Architecture: FPGA
• Core Sub-architecture: Arria, Cyclone, Stratix
• Rohs Compliant: NA
• Lead Free Status / RoHS Status: na

Chapter 4: Functional Description
Example Design
Example Design
Figure 4–4. Testbench and Example Design
© March 2009 Altera Corporation
test_complete
clock_source
pnf
Table 4–3
Table 4–3. Burst Lengths and Rates
Local Burst Length 2
For a local burst length of 2, the write latency increases by two clock cycles; the read
latency increases by one clock cycle (including checking and correction).
A partial write results in a read followed by write in the ECC controller, so latency
depends on the time the controller takes to fetch the data from the particular address.
For a single-bit error, the automatic correction of memory takes place without stalling
the read cycle (if enabled), which stalls further commands to the ECC controller,
while the correction takes place.
The MegaWizard Plug-In Manager helps you create an example design that shows
you how to instantiate and connect the DDR or DDR2 SDRAM high-performance
controller. The example design consists of the DDR or DDR2 SDRAM high-
performance controller, some driver logic to issue read and write requests to the
controller, a PLL to create the necessary clocks, and a DLL (Stratix series only). The
example design is a working system that you can compile and use for both static
timing checks and board tests.
Figure 4–4
Testbench
Example Design
Local Burst Length
shows the relationship between burst lengths and rate.
shows the testbench and the example design.
Example
Driver
1
2
High-Performance
PLL
ALTMEMPHY
Megafunction
DDR SDRAM
Controller
DDR and DDR2 SDRAM High-Performance Controller User Guide
Rate
Half
Full
DLL
Board Delay Model
Memory Burst Length
DDR SDRAM
DIMM Model
4
4
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