IPR-SDRAM/HPDDR2 Altera, IPR-SDRAM/HPDDR2 Datasheet - Page 51

• Manufacturer Part Number: IPR-SDRAM/HPDDR2
• Description: IP CORE Renewal Of IP-SDRAM/HDDR2
• Manufacturer: Altera

Specifications of IPR-SDRAM/HPDDR2

• Software Application: IP CORE, Memory Controllers, SDRAM
• Supported Families: Stratix FPGAs, Quartus II
• Core Architecture: FPGA
• Core Sub-architecture: Arria, Cyclone, Stratix
• Rohs Compliant: NA
• Lead Free Status / RoHS Status: na

Chapter 4: Functional Description
Interfaces and Signals
Figure 4–8. Half Rate Write, Native Interface Mode
Note to
(1) DDR Command and Mem Command show the command that the command signals are issuing.
© March 2009 Altera Corporation
Controller - PHY Interface (Non-AFI)
control_wdata_valid
Mem Command
DDR Command
control_dqs_burst
PHY Memory Interface
local_wdata_req
local_write_req
local_read_req
control_wdata
local_address
Figure
local_wdata
local_ready
mem_cs_n
Local Interface
mem_addr
control_be
local_size
mem_dqs
mem_dm
ddr_cs_n
mem_clk
mem_ba
mem_dq
local_be
phy_clk
ddr_ba
ddr_a
4–8:
(1)
(1)
00
1
[1]
01
[2] [3]
BBAA
02
FF
[4]
DDCC
NOP
FF
FFEE
FF
NOP
00
DDR and DDR2 SDRAM High-Performance Controller User Guide
BBAA
WR
04
0
FF
[5]
DDCC
08
FF
FFEE
[6]
00
FF
WR
00
A A B B C C D D E E F F
04
[7]
0
NOP
08
NOP
[8]
4–23