IPR-SDRAM/HPDDR2 Altera, IPR-SDRAM/HPDDR2 Datasheet - Page 29

• Manufacturer Part Number: IPR-SDRAM/HPDDR2
• Description: IP CORE Renewal Of IP-SDRAM/HDDR2
• Manufacturer: Altera

Specifications of IPR-SDRAM/HPDDR2

• Software Application: IP CORE, Memory Controllers, SDRAM
• Supported Families: Stratix FPGAs, Quartus II
• Core Architecture: FPGA
• Core Sub-architecture: Arria, Cyclone, Stratix
• Rohs Compliant: NA
• Lead Free Status / RoHS Status: na

4. Functional Description
The DDR and DDR2 SDRAM high-performance controllers instantiate encrypted
control logic and the ALTMEMPHY megafunction. The controller accepts read and
write requests from the user on its local interface, using either the Avalon-MM
interface protocol or the native interface protocol. It converts these requests into the
necessary SDRAM commands, including any required bank management commands.
Each read or write request on the Avalon-MM or native interface maps to one
SDRAM read or write command. Since the controller uses a memory burst length of 4,
read and write requests are always of length 1 on the local interface if the controller is
in half-rate mode. In full-rate mode, the controller accepts requests of size 1 or 2 on
the local interface. Requests of size 2 on the local interface produce better throughput
as whole memory burst is used.
The bank management logic in the controller keeps a row open in every bank in the
memory system. For example, a controller configured for a double-sided, 4-bank DDR
or DDR2 SDRAM DIMM keeps an open row in each of the 8 banks. The controller
allows you to request an auto-precharge read or auto-precharge write, allowing
control over whether to keep that row open after the request. You can achieve
maximum efficiency when you issue reads and writes to the same bank, with the last
access to that bank being an auto-precharge read or write. The controller does not do
any access reordering.
f
For more information on the ALTMEMPHY megafunction, refer to the
External
Memory PHY Interface Megafunction User Guide
(ALTMEMPHY).
© March 2009 Altera Corporation
DDR and DDR2 SDRAM High-Performance Controller User Guide