IPR-SDRAM/HPDDR2 Altera, IPR-SDRAM/HPDDR2 Datasheet - Page 80
IPR-SDRAM/HPDDR2
Manufacturer Part Number
IPR-SDRAM/HPDDR2
Description
IP CORE Renewal Of IP-SDRAM/HDDR2
Manufacturer
Altera
Datasheet
1.IP-SDRAMHPDDR.pdf
(88 pages)
Specifications of IPR-SDRAM/HPDDR2
Software Application
IP CORE, Memory Controllers, SDRAM
Supported Families
Stratix FPGAs, Quartus II
Core Architecture
FPGA
Core Sub-architecture
Arria, Cyclone, Stratix
Rohs Compliant
NA
Lead Free Status / RoHS Status
na
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5–8
DDR and DDR2 SDRAM High-Performance Controller User Guide
Figure 5–3 on page 5–9
and memory interfaces, together with the test complete signals.
As the data written to the memory is simply an LFSR pattern, the example driver is
able to generate expected read data from the memory to compare with that previously
written to the same address. The data on the read data bus should match that on the
write data bus during the read process.
shows the series of writes followed by reads on both the local
Chapter 5: Example Design Walkthrough
© March 2009 Altera Corporation
The Testbench Stages
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