IPR-SDRAM/HPDDR2 Altera, IPR-SDRAM/HPDDR2 Datasheet - Page 31

• Manufacturer Part Number: IPR-SDRAM/HPDDR2
• Description: IP CORE Renewal Of IP-SDRAM/HDDR2
• Manufacturer: Altera

Specifications of IPR-SDRAM/HPDDR2

• Software Application: IP CORE, Memory Controllers, SDRAM
• Supported Families: Stratix FPGAs, Quartus II
• Core Architecture: FPGA
• Core Sub-architecture: Arria, Cyclone, Stratix
• Rohs Compliant: NA
• Lead Free Status / RoHS Status: na

Chapter 4: Functional Description
Block Description
© March 2009 Altera Corporation
The blocks in
Command FIFO
This FIFO allows the controller to buffer up to four consecutive read or write
commands. It is built from logic elements, and stores the address, read or write flag,
and burst count information. If this FIFO fills up, the local_ready signal to the user
is deasserted until the main state machine takes a command from the FIFO.
Write Data FIFO
The write data FIFO holds the write data from the user until the main state machine
can send it to the ALTMEMPHY megafunction (which does not have a write data
buffer). In Avalon-MM interface mode, the user logic presents a write request,
address, burst count, and one or more beats of data at the same time. The write data
beats are placed into the FIFO until they are needed. In native interface mode, the user
logic presents a write request, address, and burst count. The controller then requests
the correct number of write data beats from the user via the local_wdata_req
signal, and the user logic must return the write data in the clock cycle after the write
data request signal.
This FIFO is sized to be deeper than the command FIFO to prevent it from filling up
and interrupting streaming writes.
Write Data Tracking Logic
This logic keeps track of how many beats of write data are in the FIFO. In native
interface mode, this logic manages how much more data to request from the user
logic and issues the local_wdata_req signal.
Main State Machine
This state machine decides what DDR commands to issue based on inputs from the
command FIFO, the bank management logic, and the timer logic.
Bank Management Logic
The bank management logic keeps track the current state of each bank. It can keep a
row open in every bank in your memory system. The state machine uses the
information provided by this logic to decide whether it needs to issue bank
management commands before it reads or writes to the bank. The controller always
leaves the bank open unless the user requests an auto-precharge read or write. The
periodic refresh process also causes all the banks to be closed.
Timer Logic
The timer logic tracks whether the required minimum number of clock cycles has
passed since the last relevant command was issued. For example, the timer logic
records how many cycles have elapsed since the last activate command so that the
state machine knows it is safe to issue a read or write command (t
also counts the number of clock cycles since the last periodic refresh command and
sends a high priority alert to the state machine if the number of clock cycles has
expired.
Figure 4–2 on page 4–2
are described in the following sections.
DDR and DDR2 SDRAM High-Performance Controller User Guide
RCD
). The timer logic
4–3