IPR-SDRAM/HPDDR2 Altera, IPR-SDRAM/HPDDR2 Datasheet - Page 58

• Manufacturer Part Number: IPR-SDRAM/HPDDR2
• Description: IP CORE Renewal Of IP-SDRAM/HDDR2
• Manufacturer: Altera

Specifications of IPR-SDRAM/HPDDR2

• Software Application: IP CORE, Memory Controllers, SDRAM
• Supported Families: Stratix FPGAs, Quartus II
• Core Architecture: FPGA
• Core Sub-architecture: Arria, Cyclone, Stratix
• Rohs Compliant: NA
• Lead Free Status / RoHS Status: na

4–30
DDR and DDR2 SDRAM High-Performance Controller User Guide
The following sequence corresponds with the numbered items in
1. The user logic requests the first read by asserting local_read_req signal, and
2. The user logic initiates a second read to a different memory row within the same
3. When the command queue is full, the controller deasserts the local_ready
4. The controller issues the first read memory command and address signals to the
5. The controller asserts the control_doing_rd signal to indicate to the
6. The ALTMEMPHY megafunction issues the first read command to the memory
7. The ALTMEMPHY megafunction returns the first data read to the controller after
the size and address for this read. In this example, the request is a burst length of 1
to local address 0x000004. This local address is mapped to the following memory
address in half-rate mode:
mem_row_address = 0x0000
mem_col_address = 0x0004<<2 = 0x0010
mem_bank_address = 0x00
bank. The request for the second write is a burst length of 1. In this example, the
user logic continues to request subsequent reads to addresses 0x000804,
0x000806, 0x000808, and 0x00080A. The controller continues to accept
commands until the command queue is full. When the command queue is full, the
controller deasserts the local_ready signal. The starting address 0x000804 is
mapped to the following memory address in half-rate mode:
mem_row_address = 0x0008
mem_col_address = 0x0002<<2 = 0x0008
mem_bank_address = 0x00
signal to indicate that the controller has not accepted the command. The user logic
must keep the read request, size, and address signal until the local_ready
signal is asserted again.
ALTMEMPHY megafunction for it to send to the memory device.
ALTMEMPHY megafunction the number of clock cycles of read data it must
expect for the first read. The ALTMEMPHY megafunction uses the
control_doing_rd signal to enable its capture registers for the expected
duration of memory burst.
1
and captures the read data from the memory.
resynchronizing the data to the phy_clk domain, by asserting the
control_rdata_valid signal when there is valid read data on the
control_rdata bus.
Refer to the "Handshake Mechanism Between Read Commands and Read
Data" section of the
(ALTMEMPHY)
for more details of this interface.
External Memory PHY Interface Megafunction User Guide
Chapter 4: Functional Description
© March 2009 Altera Corporation
Figure
Interfaces and Signals
4–11.