IPR-SDRAM/HPDDR2 Altera, IPR-SDRAM/HPDDR2 Datasheet - Page 45
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IPR-SDRAM/HPDDR2
Manufacturer Part Number
IPR-SDRAM/HPDDR2
Description
IP CORE Renewal Of IP-SDRAM/HDDR2
Manufacturer
Altera
Datasheet
1.IP-SDRAMHPDDR.pdf
(88 pages)
Specifications of IPR-SDRAM/HPDDR2
Software Application
IP CORE, Memory Controllers, SDRAM
Supported Families
Stratix FPGAs, Quartus II
Core Architecture
FPGA
Core Sub-architecture
Arria, Cyclone, Stratix
Rohs Compliant
NA
Lead Free Status / RoHS Status
na
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Chapter 4: Functional Description
Interfaces and Signals
© March 2009 Altera Corporation
Full Rate Write, Native Interface Mode—Non-Consecutive Write
Figure 4–6 on page 4–18
using the Local Interface Protocol setting set to Native interface. The figure shows
non-consecutive write-to-write requests, each of burst size 2 to sequential addresses.
In full-rate mode, the controller allows you to use burst size 1 or 2. To achieve the
highest throughput, you should use bursts of size 2, which correspond to a complete
memory burst of 4. Bursts of size 1 on the local interface are only half as efficient
because each request still corresponds to a memory burst of size 4 but only half of the
data is used.
shows write accesses with a controller in full-rate mode and
DDR and DDR2 SDRAM High-Performance Controller User Guide
4–17
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