IPS-VIDEO Altera, IPS-VIDEO Datasheet - Page 120

• Manufacturer Part Number: IPS-VIDEO
• Description: MegaCore Suite W/ 17 DSP Video/image Processing Functions
• Manufacturer: Altera
• Type: -r

Specifications of IPS-VIDEO

• Software Application: IP CORE, SUITES
• Supported Families: Arria GX, Cyclone II, HardCopy II, Stratix II
• Core Architecture: FPGA
• Core Sub-architecture: Arria, Cyclone, Stratix
• Rohs Compliant: NA
• Function: Suite of IP Functions for Video and Image Processing
• License: Initial License
• Lead Free Status / RoHS Status: na
• Lead Free Status / RoHS Status: na

5–36
Control Synchronizer
Video and Image Processing Suite User Guide
The Color Space Converter MegaCore function can process streams of pixel data of
the types shown
Table 5–17. Color Space Converter Avalon-ST Video Protocol Parameters
You can use the Control Synchronizer MegaCore function to synchronize the
configuration of other MegaCore functions with an event in the video stream. The
control synchronizer has an Avalon Video Streaming Input and Output port, which
passes through Avalon-ST Video data, and monitors the data for trigger events. The
events that can trigger the control synchronizer are the start of a video data packet, or
a change in the width or height field of a control data packet that describes the next
video data packet.
The Control Synchronizer MegaCore function also has an Avalon Master port. When
the Control Synchronizer MegaCore function detects a trigger event the MegaCore
writes data to the Avalon Slave control ports of other MegaCores. The Control
Synchronizer MegaCore function also has an Avalon Slave port that sets the data to be
written and the addresses that the data should be written to when the MegaCore
function detects a trigger event.
When the Control Synchronizer MegaCore function detects a trigger event, it
immediately stalls the Avalon-ST video data flowing through the MegaCore, which
freezes the state of other MegaCore functions on the same video processing data path
that do not have buffering in between. The Control Synchronizer then writes the data
stored in its Avalon Slave register map to the addresses that are also specified in the
register map. Once this writing is complete the Control Synchronizer resumes the
Avalon-ST video data flowing through it. This function ensures that any cores after
the Control Synchronizer have their control data updated before the start of the video
data packet to which the control data applies. Once all the writes from a Control
Synchronizer trigger are complete, an interrupt is triggered or is initiated, which is the
“completion of writes” interrupt.
Frame Width
Frame Height
Interlaced / Progressive
Bits per Color Sample
Color Pattern
Notes to
(1) For channels in parallel, the top of the color pattern matrix represents the MSB of data and the bottom represents
the LSB. For details, refer to
Parameter
Table
5–17:
(1)
inTable
Read from control packets at run time.
Read from control packets at run time.
Either.
Number of bits per color sample selected in the parameter editor.
For color planes in sequence:
For color planes in parallel:
5–17.
“Avalon-ST Video Protocol” on page
4–2.
Value
Chapter 5: Functional Descriptions
May 2011 Altera Corporation
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