IPS-VIDEO Altera, IPS-VIDEO Datasheet - Page 124

• Manufacturer Part Number: IPS-VIDEO
• Description: MegaCore Suite W/ 17 DSP Video/image Processing Functions
• Manufacturer: Altera
• Type: -r

Specifications of IPS-VIDEO

• Software Application: IP CORE, SUITES
• Supported Families: Arria GX, Cyclone II, HardCopy II, Stratix II
• Core Architecture: FPGA
• Core Sub-architecture: Arria, Cyclone, Stratix
• Rohs Compliant: NA
• Function: Suite of IP Functions for Video and Image Processing
• License: Initial License
• Lead Free Status / RoHS Status: na
• Lead Free Status / RoHS Status: na

5–40
Video and Image Processing Suite User Guide
Deinterlacing Methods
1
When you select a frame buffering mode, the Deinterlacer output is calculated in
terms of the current field and possibly some preceding fields. For example, the bob
algorithm uses the current field, whereas the weave algorithm uses both the current
field and the one which was received immediately before it. When producing one
output frame for every input field, each field in the input frame takes a turn at being
the current field.
However, if one output frame is generated for each pair of interlaced fields then the
current field moves two fields through the input stream for each output frame. This
means that the current field is either always a F0 field (defined as a field which
contains the top line of the frame) or always a F1 field.
The Deinterlacer MegaCore function does not currently use the two synchronization
bits of the interlace nibble. (Refer to
frame rate = output frame rate, the choice of F0 or F1 to be the current field has to be
made at compile time. The deinterlacing algorithm does not adapt itself to handle PsF
content.
Figure 5–21
with frame buffering.
Figure 5–21. Deinterlacer Block Diagram with Buffering in External RAM
Note to
(1) There can be one or two Avalon-MM masters connected to the Memory Reader.
The Deinterlacer MegaCore function supports four deinterlacing methods:
■
■
■
■
Bob with scanline duplication
Bob with scanline interpolation
Weave
Motion-adaptive
Avalon-ST Input
Figure
Avalon-MM Master
5–21:
(din)
shows a simple block diagram of the Deinterlacer MegaCore function
(write_master)
Memory
Writer
Arbitration Logic
SDRAM
DDR2
“Control Data Packets” on page
Memory
Reader
Avalon-MM Master
(read_master)
Deinterlacing
Algorithm
Chapter 5: Functional Descriptions
May 2011 Altera Corporation
4–7.) When input
Avalon-ST Output
(dout)
Deinterlacer